disable_anatop_clocks in clk-imx6q.c causes hang for lpddr2 board.

[gaun]

Hi,

I have a custom board which has an lpddr2 working at 200MHz. (Tested with android kitkat).  I am trying to boot the NXP provided Android Marshmallow with the necessary changes needed for our board. I have setup the DCD file by running the LPDDR2 stress test calibration. The only change I did in the DCD file is to set the

DATA 4, 0x020c4018, 0x000e0324 for 200MHz instead of DATA 4, 0x020c4018, 0x00060324 for the 400 MHz.

When I enabled earlyprintk and debugging in the kernel I found that it gets stuck near CCM initialization (tracing from clk.c to clk-imx6q.c). I finally found that it hangs at disable_anatop_clocks in clk-imx6q.c). If I set the reg to 0x8080 in the check where IMX6QDL_CLK_PREIPH_PRE parent is IMX6QDL_CLK_PLL2_PFD2_396M which fails then the board boots up with binder throwing timerqueue_add error in android and finally crashes.

After searching on the net I find in the mailing list that the ldb glitchless bug initialization was recently added. In my case I think it is disabling PLL2PFD2 which is used as memory clock (divided by 2) as per the DCD value shown above.

Reference: http://www.spinics.net/lists/arm-kernel/msg486782.html

For reference I will paste the kernel log below:

Starting kernel ...
Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpu
Initializing cgroup subsys cpuacct
Linux version 3.14.52-141398-gad65770-dirty (xxxx@xxxxx) (gcc version 4.9.x-google 20140827 (prerelease) (GCC) ) #33 SMP 
PREEMPT Sun Aug 21 17:15:17 IST 2016
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: Freescale i.MX6 DualLite Roche Solaris HH Board
bootconsole [earlycon0] enabled
cma: CMA: reserved 320 MiB at 2a000000
Memory policy: Data cache writealloc
PERCPU: Embedded 9 pages/cpu @ef729000 s13312 r8192 d15360 u36864
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 522511
Kernel command line: console=ttymxc0,115200 earlyprintk
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1732660K/2096124K available (10724K kernel code, 789K rwdata, 3820K rodata, 593K init, 766K bss, 363464K reserved, 1317884K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0e3c550   (14546 kB)
      .init : 0xc0e3d000 - 0xc0ed1400   ( 593 kB)
      .data : 0xc0ed2000 - 0xc0f976ac   ( 790 kB)
       .bss : 0xc0f976ac - 0xc1057024   ( 767 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Preemptible hierarchical RCU implementation.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
L310 cache controller enabled
l2x0: 16 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x32050000, Cache size: 512 kB

Can somebody help me in solving this issue. How do I make the IMX6QDL_CLK_PREIPH_PRE parent of IMX6QDL_CLK_PLL2_PFD2_396M?

[igorpadykov]

Hi Gautam

for such case in nxp 3.14.52  clk-imx6q.c function  disable_anatop_clocks()

linux-2.6-imx.git - Freescale i.MX Linux Tree

there is check:

	if (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) ==
	clk[IMX6QDL_CLK_PLL2_PFD2_396M])

could you test with nxp official bsp on link below

i.MX 6 Series Software and Development Tool|NXP

Best regards

igor

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[gaun]

I am testing with the official BSP's. Could you please let me know how to select a 200MHz clock for my lpddr2?

[igorpadykov]

one can check process for ldb switch in EB821 document

LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines

http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf 

also may be useful to look at i.MX6S lpddr2 settings
https://community.freescale.com/docs/DOC-94790

Best regards
igor

[gaun]

igor,

I have gone through the document and it is already implemented in the driver. What is not provided is how to prevent the mmdc clock from being put off. Could you please answer the above question of setting the clock parent?

[igorpadykov]

if board did not hang previously with android kitkat, then

one can skip this ldb patch, since not all chips are affected with it.

For bsp customization one can apply to NXP Professional Services:

http://www.nxp.com/support/nxp-professional-services:PROFESSIONAL-SERVICE
Pro-Support contact www.nxp.com/prosupport

Best regards
igor

[gaun]

I cannot skip the ldb patch. It is what is provided in your base source code. I just need to make the clk as parent. Does anybody in NXP know how to do this?

[gaun]

Hi Igor,

The clock parent is not set. In the 'if' 'else' statement I had put a log in the 'else' block and the log comes up there. Hence the clock parent is not set. When I tried to set it, it crashes. I have not tried more but I will try again. Apart from that do you have any idea where to put it? Also the lpddr2 and the ddr uses the pfd2 by default. I am not sure why the clock parent is not set as default.

Thanks,

Gautam.