ddr3 calibration error with IMX6UL custom board

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ddr3 calibration error with IMX6UL custom board

473 Views
kr90911
Contributor III

Hi,All

We made some custom board with IMX6UL chip and  MT41K64M16-125 SDRAM,and encountered problems while doing ddr calibration on board by  ddr_stress_tester_v3.00. There are calibration log as follow:

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000870
SRC_SBMR2(0x020d801c) = 0x02000001
============================================

ARM Clock set to 528MHz

============================================
DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 13, col size: 10
Chip select CSD0 is used
Density per chip select: 128MB
============================================

Current Temperature: 32
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
MPWLHWERR register read out for factory diagnostics:
MPWLHWERR PHY0 = 0x00000087

HW WL cal status: no suitable delay value found for byte 1
Write leveling calibration completed but failed, the following results were found:
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F0000
Write DQS delay result:
Write DQS0 delay: 0/256 CK
Write DQS1 delay: 31/256 CK


Error: failed during write leveling calibration

The script I used can make calibration success on official board IMX6ULEVK.

Hope you can give me some advice about what happen to my board.

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7 Replies

128 Views
kr90911
Contributor III

Hi,all.

The problem solved after I replace the ddr3 density from 128 to 256 MB.

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128 Views
kr90911
Contributor III

Hi all,

I measured some pin with oscilloscope showed as follow:

DRAM_SDCKE0= 0V

DRAM_SDCKE1=   0V,when doing calibration it came to 1.37V for about 16ms.

DRAM_VREF=        0.68V

DRAM_1V35=         1.37V

DRAM_RESET_B= 0V

XTALI=                    22.5MHz

RTCXTALI=             33.3kHz

DRAM_RESET_B was always be 0V when downloading script or doing calibration.

If I am not misunderstanding,according to Hardware Development Guide for the i.MX 6UltraLite Applications Processor ,

DRAM_RESET_B should go High when board getting calibration.

I'll keep finding how the bug comes up.

If someone know how to deal with it,leave some comment,please.

Thanks.

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128 Views
igorpadykov
NXP TechSupport
NXP TechSupport

one can try to write/read to memory with jtag checking signals with

osciloscope. Use  jesd79 jedec ddr3 specificaton for signal description.

Best regards
igor

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128 Views
kr90911
Contributor III

Hi,igor.

Thanks for your reply.

I just retest DRAM_RESET_B and foud it goes High when the script downloaded in board.

 

I ran Memory Read/Write function and it worked,logs showed as below:

0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x80000000: 0xE75BEBF7 0xD3FEEBBF 0xAD779B7C 0xAF66D3EE
0x80000010: 0x40A34A96 0xF55ECBC2 0xE6FCEFD4
0x80000020: 0xFDB055AE 0x176FBCBB 0x9BF3377F 0x9BD32ABD
0x80000030: 0xA4B5E7A5 0x658BE9EF 0x5ABB639E 0x1F9FDFF6
0x80000040: 0xFC799FBF 0xDFE55F2B 0xEEAC9DB9 0xB8FE8912
0x80000050: 0xB7FEC9CC 0xBDDEAAFF 0xE8BFDF6E 0xD7BB75FD
0x80000060: 0xB4819552 0x87FE8117 0xC7DFF563 0xA57A84FD
0x80000070: 0x773619BA 0xFF2F6778 0x7FFFFFFD 0xBD35FFB7
memory read is done
addr=0x80000000,data=0xE75BEBF8

Success to write address 0x80000000

0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x80000000: 0xE75BEBF8 0xD3FEEBBF 0xF6BE6DB5
0x80000020: 0xFDB055AE 0x176FBCBB 0x9BF3377F 0x9BD32ABD
0x80000030: 0xA4B5E7A5 0x658BE9EF 0x5ABB639E 0x1F9FDFF6
0x80000040: 0xFC799FBF 0xDFE55F2B 0xEEAC9DB9 0xB8FE8912
0x80000050: 0xB7FEC9CC 0xBDDEAAFF 0xE8BFDF6E 0xD7BB75FD
0x80000060: 0xB4819552 0x87FE8117 0xC7DFF563 0xA57A84FD
0x80000070: 0x773619BA 0xFF2F6778 0x7FFFFFFD 0xBD35FFB7
memory read is done

Memory read and write is work,but ddr calibration still failed.

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128 Views
kr90911
Contributor III

Hi,igor

Thank for your response.

I captured a signal showed as followed when ddr test tool doing calibration.

The signal from DRAM SD_CLK0P:

DRAM_SDCLK0P4.jpg

The signal from SDQS0P and SDQS1P:

DRAM_SDQS12P2.jpg

I think calibration failed because delay time of SDQS1 as log showed before.

Is there any possible way to fix delay time of SDQS1?

Thanks and best regards.

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128 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi west

this may be caused by hardware, suggest to check it with oscilloscope using

Hardware Development Guide for the i.MX 6UltraLite Applications Processor

Best regards
igor
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-----------------------------------------------------------------------------------------------------------------------

128 Views
kr90911
Contributor III

Hi,igor.

Thanks for your support.

I found some detail about this issue.

I hope you can look at this.

Thanks.

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