Hi,All
We encountered some question in DDR3.We have produced about 1 thousand boards,and we got several (5~6) board fail to boot from EMMC,after checked the DDR3,we found ddr3 caused the booting failing.
our DDR3 device is :
I used the ddr stress test tool v2.6 to test one of our faulted custom board，I got some strange results in HW write leveling process.
ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F001F
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001F001F
Write DQS delay result:
Write DQS0 delay: 31/256 CK
Write DQS1 delay: 31/256 CK
Write DQS2 delay: 31/256 CK
Write DQS3 delay: 31/256 CK
Write DQS4 delay: 31/256 CK
Write DQS5 delay: 31/256 CK
Write DQS6 delay: 31/256 CK
Write DQS7 delay: 31/256 CK
Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x11111111
. HC_DEL=0x00000001 result[01]=0x11111111
. HC_DEL=0x00000002 result[02]=0x11111111
. HC_DEL=0x00000003 result[03]=0x11111111
. HC_DEL=0x00000004 result[04]=0x11111111
. HC_DEL=0x00000005 result[05]=0x11111111
. HC_DEL=0x00000006 result[06]=0x11111111
. HC_DEL=0x00000007 result[07]=0x11111111
. HC_DEL=0x00000008 result[08]=0x11111111
. HC_DEL=0x00000009 result[09]=0x11111111
. HC_DEL=0x0000000A result[0A]=0x11111111
. HC_DEL=0x0000000B result[0B]=0x11111111
. HC_DEL=0x0000000C result[0C]=0x11111111
. HC_DEL=0x0000000D result[0D]=0x11111111
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.
Error: failed during ddr calibration
The DQS group's write leveling delay results is the same :31/256 CK delay. the nomarl board 's results is below:
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x004E004E
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0041004A
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x002B0029
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x002D0041
Write DQS delay result:
Write DQS0 delay: 78/256 CK
Write DQS1 delay: 78/256 CK
Write DQS2 delay: 74/256 CK
Write DQS3 delay: 65/256 CK
Write DQS4 delay: 41/256 CK
Write DQS5 delay: 43/256 CK
Write DQS6 delay: 65/256 CK
Write DQS7 delay: 45/256 CK
I read the manual " 45.11.6.1 Hardware Write Leveling Calibration"
every DQS write leveling should repeat step 5~7 and adds 1/8 cycle delay between DQS and clk every times,then fine tuning must be executed to find precise delay value ,the resolution of the tuning is 1/256 clk.
What clues can we get through this result?
does the 31/256 results mean that write leveling only execute the first 5~7 step then the ddr device sampled the CLK and got the transition from 0 to 1,then tuining the result to 31cycles?
