ddr memory map

[mrlantz]

When configure the ddr memory map I can see that most of the configuration with 2x512MB density set CS0_END to 768 MB. If I set it to 512 MB that are logic I get some strange behavior when accessing higher addresses. Why should it be 768 MB!?

Is it possible to change CS1 start address or will it automatically start after CS0_END? If so than I cannot understand why 768 MB are used for CS0_END.

[AnsonHuang]

Hi, Johan

    There has been soch topic in imx community, I pasted the picture as below, hope it helps. And I do NOT think CS1 will auto start after CS0_END. If I remembered correctly, for DDR3, MMDC only support single channel. If you have 2*512MB density, then the CS0_END should be as below:

(0x10000000 + 0x40000000) / 0x2000000 - 1 = 0x27.

    What is the value of your CS0_END? 768MB means the value is 0x17? If you set it to 512MB, then I think when you access higher address, it will just wrap from the start address, can you have a try to confirm?

[mrlantz]

The RM states that CS1 should be defined by CS0_END. If you are not sure could you please check this?

[mrlantz]

It would be good if the RM has the same description than the PP. The RM dose not describe that the start address should be added to the calculation. Maybe you should consider to update the spec.