Hi team,
Need your help for the following case:
I have made changes in dtsi file to get codec registered. But facing an issue.
Changes:
imx8mm-evk.dtsi>>>>>>>
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
Created I2c4 node:
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
tlv320aic3x: codec@18 {
compatible = "ti,tlv320aic3x","ti,tlv320aic3104";
reg = <0x18>;
#sound-dai-cells = <0>;
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
/* Regulators */
DRVDD-supply = <®_3p3v>;
AVDD-supply = <®_3p3v>;
IOVDD-supply = <®_3p3v>;
DVDD-supply = <®_1p8v>;
};
};
Error through logs:
[ 2.789721] imx8mm-pinctrl 30330000.pinctrl: pin MX8MM_IOMUXC_I2C4_SCL already requested by 30a50000.i2c; cannot claim for 33800000.pcie
[ 2.795695] pps pps0: new PPS source ptp0
[ 2.796576] mmc0: CQHCI version 5.10
[ 2.796953] mmc1: CQHCI version 5.10
[ 2.796999] sdhci-esdhc-imx 30b50000.mmc: Got CD GPIO
[ 2.802020] imx8mm-pinctrl 30330000.pinctrl: pin-139 (33800000.pcie) status -22
[ 2.802031] imx8mm-pinctrl 30330000.pinctrl: could not request pin 139 (MX8MM_IOMUXC_I2C4_SCL) from group pcie0grp on device 30330000.pinctrl
Is there any way to resolve this issue?
Thanks.
Hi Divyesh
for "MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B" conflict one can try to reassign PCIE1_CLKREQ_B to UART4_RXD (ALT2), described on
p.1267 Table 8-1. Muxing Options i.MX 8M Mini Applications Processor Reference Manual
Best regards
igor
Hi Igor,
I have replaced :
- MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */
+ MX8MM_IOMUXC_I2C4_SCL_UART4_RXD 0x61 /* open drain, pull up */
But I cannot find any MX8MM_IOMUXC_I2C4_SCL_UART4_RXD defined register definition in imx8mm-pinfunc.h or nowhere.
Is there any way to confirm that actually we are using PCIE1 in our board or not? If not so can i make it status as disabled.
Thanks.
MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B
Best regards
igor
Hi Igor,
After making following changes in dtsi file device is still rebooting continuously.
Chnages:
pinctrl_pcie0: pcie0grp {
fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
Serial Logs:
[ 2.782368] imx6q-pcie 33800000.pcie: supply epdev_on not found, using dummy regulator
[ 2.788066] mmc0: CQHCI version 5.10
[ 2.788415] pps pps0: new PPS source ptp0
[ 2.788509] mmc1: CQHCI version 5.10
[ 2.788557] sdhci-esdhc-imx 30b50000.mmc: Got CD GPIO
[ 2.790665] imx6q-pcie 33800000.pcie: EXT REF_CLK is used!.
[ 2.819694] libphy: fec_enet_mii_bus: probed
[ 2.822311] mmc1: SDHCI controller on 30b50000.mmc [30b50000.mmc] using ADMA
[ 2.828156] fec 30be0000.ethernet eth0: registered PHC device 0
[ 2.847274] imx-drm 32c00000.bus:display-subsystem: bound imx-lcdif-crtc.0 (ops lcdif_crtc_ops)
[ 2.856160] imx_sec_dsim_drv 32e10000.mipi_dsi: version number is 0x1060200
[ 2.862174] imx6q-pcie 33800000.pcie: PCIe PLL lock timeout
[ 2.863209] imx_sec_dsim_drv 32e
Thanks Igor.
One more doubt. Instead of reassigning PCIE1_CLKREQ_B to UART4_RXD. can we make changes in I2c4 pincontrol ?
PCIe1 is already in use . I have created i2c4 node newly in dtsi file. so might be it causing an issue?
Thanks