configure the ksz8765 5 port Ethernet switch

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configure the ksz8765 5 port Ethernet switch

21,469 Views
pavansingpatil
Contributor I

Hello,

we have custom board based on imx6sx connected with ksz8765 switch over spi bus using rgmii interface. we have enabled the fixed link driver in kernel and also configure same in dts file. Port 5 of the switch is connected to imx6sx MAC interface.

device tree configuration:

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "mii";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
fixed-link = <0 1 100 0 0>;
phy-supply = <&reg_vref_3v3>;
status = "okay";
};

kernel logs:

fec 2188000.ethernet (unnamed net_device) (uninitialized): Invalid MAC address: 00:00:00:00:00:00
fec 2188000.ethernet (unnamed net_device) (uninitialized): Using random MAC address: 7e:20:8b:ff:4b:22
libphy: fec_enet_mii_bus: probed
fec 2188000.ethernet eth0: registered PHC device 0
fec 2188000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=fixed-0:00, irq=-1)
fec 2188000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off

we could see RX packets are 0, and Tx packet are also in queue.

eth0 Link encap:Ethernet HWaddr XX:XX:XX:XX:XX:XX 
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:7538 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:828904 (809.4 KiB)

there is spi driver to configure switch over spi for ksz8995...but it should work for ksz8765 after minor modification as chip id and family id is same.

linux-fslc/spi_ks8995.c at 4.1-2.0.x-imx · Freescale/linux-fslc · GitHub 

spi-ks8995 spi3.2: chip family id mismatch: expected 0x87 but 0x00 read
mx51_ecspi_clkdiv: fin: 60000000, fspi: 48000000, post: 0, pre: 1
mx51_ecspi_clkdiv: fin: 60000000, fspi: 48000000, post: 0, pre: 1
spi-ks8995 spi3.2: unsupported chip id for KSZ8795 family: 0x00

but it always reads 0.

Thanks in advance.

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pavansingpatil
Contributor I

right driver is not getting correct data, but i guess driver is just for switch configuration using spi bus.

Do you think Ethernet driver fec_main.c need any modification to detect switch phy using spi bus? or it should work with fixed link driver?

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pavansingpatil
Contributor I

we are able to resolve spi communication issue, now can read/write switch resistor using spi bus. the problem was fec driver ignores the reset flag polarity and always works on active low.

we have configured switch in mii mode and now we see proper 25 MHz clk on ENET_RX_CLK  and RX_ENET1_TX_CLK .

eth0   Link encap:Ethernet  HWaddr XX::XX:XX:01:1b:b9 
          inet6 addr: fe80::204:9fff:fe01:1bb9/64 Scope:Link
          inet6 addr: fd00:1:2:3:204:9fff:fe01:1bb9/64 Scope:Global
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:4189 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:460514 (449.7 KiB)

lo        Link encap:Local Loopback 
          inet addr:127.0.0.1  Mask:255.0.0.0
          inet6 addr: ::1/128 Scope:Host
          UP LOOPBACK RUNNING  MTU:65536  Metric:1
          RX packets:163 errors:0 dropped:0 overruns:0 frame:0
          TX packets:163 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:0
          RX bytes:12460 (12.1 KiB)  TX bytes:12460 (12.1 KiB)

imx6 side MAC works fine as I tried loopback and and also localhost ping as you can see lo interface statistics. But we are still having issue with communication as you can see TX packets on eth0 interface but no response from phy. As mentioned earlier we are using fixed link driver as phy is not connected using normal mdio bus.

This is my dmesg output

## dmesg | grep fec
libphy: fec_enet_mii_bus: probed
fec 2188000.ethernet eth0: registered PHC device 0
fec 2188000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=fixed-0:00, irq=-1)
fec 2188000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off 

we have verified Clk and Tx data signal on oscilloscope and we some data going out on TX data lines.

so is there any modification required in fec driver to make it work? Thanks in advance.

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igorpadykov
NXP Employee
NXP Employee

if there is no response from phy (RX data) one can check phy registers

(dumping them and rechecking with phy datasheet), as incoming data from any port

should appear on port connected to i.mx too. The same one can with reset flag polarity,

printf corresponding gpio data in driver.

Also may be useful to look at linux documentation on

linux-imx.git - i.MX Linux Kernel 

linux-imx.git - i.MX Linux Kernel 

Best regards
igor

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pavansingpatil
Contributor I

Hi igor,

phy register looks right after rechecking with ksz8765 datasheet. Now we have almost resolved all hardware issues. we could ping between port3 and port4 of the switch. And we see proper signal on Tx and Rx pins of port 5. I have assigned static ip to my eth0 interface but still i can't ping to port 3 or port 4 and vice versa from imx6 side. I have not enabled any phy driver on imx6 side. Do we need any phy driver for communication or fixed link phy driver is enough?

eth0 Link encap:Ethernet HWaddr XX:XX:XX:01:1b:b9
inet addr:192.168.1.5 Bcast:192.168.1.255 Mask:255.255.255.0
inet6 addr: fe80::204:9fff:fe01:1bb9/64 Scope:Link
inet6 addr: fd00:1:2:3:204:9fff:fe01:1bb9/64 Scope:Global
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:28 errors:0 dropped:0 overruns:0 frame:0
TX packets:111 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:4734 (4.6 KiB) TX bytes:14353 (14.0 KiB)

Regards,

--Pavan

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lvmh
Contributor I

Hi  pavansingpatil,

Have you solved the problem?   I have a similar problem in debugging ksz8794.

I used fixed-link ,With a fixed connection, you can find the device, but the network is not available .

I used  dsa, but I didn't find success when mdio looked for equipment in dsa.

I can measure the waves of tx and rx.I guess the reason for this problem is that the switch chip is a MAC, and the CPU needs to recognize phy.

Can you give me some advice? thanks!

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