clock source selection for i.mx6 parallel lcd port with 205MHz pixel clock

[lonsn]

Hi,

I connected a RGB to eDP adapter board with parallel lcd port of a nitrogen6_max i.mx6 eval board. The required paralled lcd port pixel clock is 205MHz for 2048x1536 retina panel. We can't see any image from the LCD panel. If we decrase to 800x400 resolution, then image displayed in LCD panel although it is disordered caused by uncorrect resolution. So we doubt the 205MHz clock output is not good in the paralled lcd port. Which pll clock source is most suitable for this ipu0_di0 clock? Any other quality improvement for the parallel port clock and data from hardware/software?

We use android 5.0/kernel 3.10. Current ipu clock settings are as below:

	imx_clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
	imx_clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
	imx_clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
	imx_clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
	imx_clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
	imx_clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
	imx_clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
	imx_clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);

[lonsn]

After change the DI port speed and strength, the edp screen power on. But the quality is not very good and has some noise.

Also the pixel format is changed to RGB565 while I set RGB24 in kernel command line and dts file.

[gary_bisson]

Hi,

Sorry for the late reply, could you share your device tree, your kernel serial output and the clock tree.

For the clock tree, the easiest way is to copy/paste the output of "cat /sys/kernel/debug/clk/clk_summary" into pastebin.com.

Regards,

Gary