Hello
I attached spi device to imx6q.
(spi dev was wired spi1)
pinmap is bellow
OLED_SCLK -----CSI0_DAT4
OLED_SDIN -----CSI0_DAT5
OLED_D_C/ -----CSI0_DAT6
OLED_CS/ -----CSI0_DAT7
CSI0_DAT4 ALT2 ECSPI1_SCLK
CSI0_DAT5 ALT ECSPI1_MOSI
CSI0_DAT6 ALT ECSPI1_MISO
CSI0_DAT7 ALT ECSPI1_SS0
dts is bellow
ecspi1: ecspi@02008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_ECSPI1>,
<&clks IMX6QDL_CLK_ECSPI1>;
clock-names = "ipg", "per";
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio5 25 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
/*status = "okay";*/
status = "okay";
spidev0: spi@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spidev";
reg = <0>;
spi-max-frequency = <2000000>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x1b0b0
>;
};
but clock signal does not output.
does my dts wrong?
or do I need to set additional setting?
With best regards,
villager
HELLO @Yuri
my EVB is i.MX6Q, real target is i.MX6S/DL
There is not much difference between these two, so I wrote them in confusion.
The reason the clock does not tx is because there is no SPI clock setting.
According to the chip manual (IMX6SDLRM Rev. 1, 04/2013),
the PLL should be divided by /8 and /1.
After booting, I set the following additional settings in linux application,
and the clock signal came out normally.
/* 2nd : change clock Register (CCM_CCOSR) */
/* chip manual : 18.6.21 CCM Clock Output Source Register (CCM_CCOSR) */
setting=0x0;
#define CLK01_SEL ( 1<<3 | 0<<2 | 1<<1 | 1<<0) //1011 ahb_clk_root
#define CLK01_DIV ( 1<<6 | 1<<5 | 1<<4) //111 divide by 8
#define CLK01_EN ( 0<<7 )
#define CLK_OUT_SEL ( 1<<8 )
#define CLK02_SEL ( 0<<20 | 1<<19 | 1<<18 | 1<<17 | 0<<16) //01110 osc_clk
#define CLK02_DIV ( 0<<23 | 0<<22 | 0<<21) //111 divide by 8
#define CLK02_EN ( 0<<24 )
setting=(setting | CLK01_SEL);
setting=(setting | CLK01_DIV);
setting=(setting | CLK01_EN);
setting=(setting | CLK_OUT_SEL);
setting=(setting | CLK02_SEL);
setting=(setting | CLK02_DIV);
setting=(setting | CLK02_EN);
read_reg=0;
mmap_ioctl((unsigned long)&CCM_CCOSR, &read_reg, MMAP_RD);
if(read_reg != setting) {
printf("@%p(CCM_CCOSR) change property 0x%x->0x%x\n"
, (void *)&CCM_CCOSR, read_reg, setting);
mmap_ioctl((unsigned long)&CCM_CCOSR, &setting, MMAP_WR);
}
thank you.
