adv7181 on i.mx6 and Data_EN question

[zhouwei]

Hello,

     I am using adv7181 to convert RGB signal ,but facing some problem.  I use adv7181 to convert 800*600 rgb signal to 4:2:2 Ycbcr signal. I'm sure adv7181 is correctly configured because i have used an oscilloscope to measure output of adv7181, signals like hsync/vsync/data_en are all right.

     I config CSI0 work in gated clock mode. Cause imx6q request Hsync to be high when line data is valid, i connect Data_EN signal(output from ADV7181)  to CSI0's Hsync pin, and just leave CSI0's data_en pin dangling.

First problem:

imx6q caputure all data including vaild data when Hsync is hign and the invaild data when Hsync is low. i check all register but can not find any mistake. Here is the register:

     IPU_CONF:                     0X00000760

     CSI0_SENS_CONF:          0X0400CA00

     CSI0_SENS_FRM_SIZE:   0X0257031F

     CSI0_ACT_FRM_SIZE:      0X0257031F

     CSI0_OUT_FRM_CTRL:     0X00000000

     CSI0_TST_CTRL:              0X00000000          

     CSI0_CCIR_CODE_1:       0X00000000

     CSI0_CCIR_CODE_2:       0X00000000

     CSI0_CCIR_CODE_3:       0X00000000

     CSI0_DI:                          0XFFFFFFFF

     CSI0-SKIP:                      0X00000000

     CSIO_CPD_CTRL:           0X00000000

Second problem:

Since imx6q caputure all data including vaild data and invaild data. I programme to choose the vaild data and find that imx6q does not capture valid data in correct timing.Here is the image that imx6q captured:

while the input image is like this:

Besides,i am really confuse about date_en, the datasheet does not mention how should the waveform of data_en should be. But if i invert the data_en signal ,the imx6q would not capture any data.

Any help would be greatly appreciated.

Thanks,

zhou

[florianpantalea]

Hello,

I also had a hard time with image acquisition in gated clock mode and share my feedback.

DATA_EN is definitely necessary and should be driven to the level matching its polarity in CSI_SENS_CONF to enable acquisition. See also Re: imx6 support for 8-bit RAW camera

For the gated clock mode, I have a different figure than yours: reference manual Rev. 1, 04/2013 figure 37-17 on page 2759. CSI only requires pulses at the beginning of the frame and its lines. It doesn't matter if the pulse ends before frame end and line end. The reason is CSI determines frame and line ends with sizes in CSI_SENS_FRM_SIZE.

I would say that with a parallel output sensor or ADV718x device, the connections are:

• SENSOR_VSYNC with CSI_VSYNC
• SENSOR_HSYNC with CSI_HSYNC
• SENSOR_PCLK with CSI_PCLK
• CSI_DATA_EN = 1 if CSI_DATA_EN_POL=0 or CSI_DATA_EN = 0 if CSI_DATA_EN_POL=1

Florian

[igorpadykov]

Hi zhou

ADV7180 should be in BT656 mode (with embedded HSYNC,VSYNC),

please check below

Re: ADV7181 on IMX6Q board

Regarding data_en one can pull-up it internally and select necessary

settings with IPUx_CSI0_SENS_CONF bit CSI0_DATA_EN_POL

Best regards

igor

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[zhouwei]

HI,igor

               Since the input of adv7181 is vga signal from PC, component processor (CP) mode is needed to convert this signal. But CP do not support BT656 output.

[igorpadykov]

Hi zhou

you can try to use mxc_v4l2_capture, as below

https://community.freescale.com/message/423400#423400

~igor

[zhouwei]

Could you tell me where i can find more information about "mxc_v4l2_capture" and "test_unit" they mentioned in this URL ?

[igorpadykov]

Hi zhou

just some small comments:

- there is no possibility i.MX6 to receive VGA signal

- supported i.MX6 IPU CSI formats can be found in

Table 66. Camera Input Signal Cross Reference, Format, and Bits Per Cycle IMX6DQCEC

- "mxc_v4l2_capture" and "test_unit" can be found in ltib, select imx-test package and build ltib

~igor

[zhouwei]

HI, igor

      Maybe i did not make it clear.

     The input signal of i.MX6 is not VGA signal. VGA signal has been conveted into 16bits YUV4:2:2 signal by ADV7181. It means the i.mx6 will receive 16bits YUV4:2:2 signal. In the datasheet IMX6DQCED ,it matchs the situation YCbCr6  16bits 1 cycle.

[igorpadykov]

Hi zhou

below you can find answer from IPU expert for this mode

https://community.freescale.com/thread/312214

In general you can use generic mode as described below

https://community.freescale.com/message/331888

~igor

[zhouwei]

More information

     When I set  IPU2_CSIx_HSYNC high all time, imx6 could not capture any data. But if i set  IPU2_CSIx_HSYNC as normal signal output from adv7181, imx6 could caputre data. So i think it is the rising edge of IPU2_CSIx_HSYNC that trigger imx6 starting to capture data, not high level. Maybe there is something wrong in the datasheet.

[igorpadykov]

Hi zhou

yes you are correct, capture occurs on HSYNC edge as confirmed below

Re: IPU v3 CSI0, HSYNC and DATA_EN questions in gated clock mode.

also I think your case similar to

Re: OV7740 camera on I.MX6 using CSI0 in BT.656 mode

Best regards

igor

[zhouwei]

Hi, igor

     Thank you very much for your supporting and guidance.

     In my case, there is no possibility to input BT656 signal to IMX6 because of ADV7181. And i have to config imx6 to work in gated clock mode. Now the only problem is imx6 do not stop capturing data when a line ends as ZHU YANG's Question2 in IPU v3 CSI0, HSYNC and DATA_EN questions in gated clock mode.  Unfortunatly, no one gives an answer to him. I hope you are the one who give an accurate answer for this problem.

     Thank you again for your help.

[igorpadykov]

Hi zhou

I think you can also find gate mode example in SDK

ipu_csi.c i.MX 6Series Platform SDK : Bare-metal SDK

i.MX6_SABRE_SDP_DESIGNFILES : Design files, including hardware schematics,

~igor

[zhouwei]

HI igor

    After a lot of testing, i found that the real problem is imx6 don't stop capturing data while Hsync goes to low at the end of line. Could you give me some advice?

[zhouwei]

HI igor

      In this discussion https://community.freescale.com/thread/312214, it is said "current Freescale Linux BSP doesn't support 16-bit input through CSI (although the IC supports)." I think it do not make sense, because i had made relevant changing in kernel to match my case.

     Whatever, in my case, i.mx6 would receive 16bits 4:2:2 YUV signal while working in gated clock mode.I had used an oscilloscope to measure Hsync Vsync and pixel clock. Those signals are all matched to the timing diagram that is shown in IMX6DQCEC(section 4.11.10.2.2 Gated Clock Mode). And it says"

Pixel clock is valid as long as IPU2_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. IPU2_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream.

What confused me is that imx6 would capture all data despite Hsync is high or low.

What's more, as you mentioned before,"Regarding data_en one can pull-up it internally and select necessary settings with IPUx_CSI0_SENS_CONF bit CSI0_DATA_EN_POL".Could you tell me how to pull_up it? What does "necessary" exactly means? And i would like to make it clear whether i should config IPU2_CSI0_DATA_EN  works in GPIO mode or data_en mode.

Thank you very much!

[zhouwei]

Hi,igor

     I think my situation is different from Daiane Angolini"s. In his case ,he use adv7180 to convert signal output from camera, so the signal should be PAL or NTSC standard. And adv7180 is able to convert PAL or NTSC to BT656 mode. But i am going to convert signal output from PC, so the signal  is VGA signal. Adv7181 is not able to convert it to BT656 mode. So in my case , i config adv7181 to convert VGA signal to 16 bit YUV4:2:2. It is feasible theoretically. But as shown before, the image imx6q captured is not right.