about i.MX6 PCIe cache coherency

[masamiyasui]

In i.MX6Q PCIe End Point,  if cache is enabled  in the inbound area, I think that cache invalidate is necessary before and after writing from Root Complex to this area.
How can End Point know the timing of these cache invalidate?

Without these cache invalidate, End Point could not read the data which Root Complex wrote to this area.

[Yuri]

Hello,

  I.MX6 does not support cache coherency (in hardware). Therefore it

may be recommended to configure the PCIe memory area as non-cached,

if several bus masters can access it.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[masamiyasui]

Thank you very much for your quick response.