Yocto 3.0 imx8qxp support pwm2

[zhengguang_yang]

Hello:

I'm using imx8qxp, Yocto 3.0

I am working with a custom board that requires UART1_RTS_B to be used as a PWM output. 

But I did not see any nodes in these files for the LSIO PWM modules and I did not see them enabled in the device tree for the IMX8QXP MEK. 

[igorpadykov]

Hi Zhengguang

patch was sent you via mail.

Best regards
igor

[zhengguang_yang]

Hi Igorpadykov:

Thank you for your reply.

This patch can be used in yocto 2.5, but the code structure of yocto 3.0 changes greatly, such as drivers/clk/imx/clk-imx8qxp.c. It seems that this patch cannot be used directly in yocto 3.0.

[zhengguang_yang]

The kernel version we use is 5.4.

Part of the code of drivers/clk/imx/clk-imx8qxp.c is as follows

static int imx8qxp_clk_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id =
of_match_device(imx8qxp_match, &pdev->dev);
struct device_node *ccm_node = pdev->dev.of_node;
int ret;

ret = imx_clk_scu_init(ccm_node, of_id->data);
if (ret)
return ret;

/* ARM core */
imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
imx_clk_scu("a53_clk", IMX_SC_R_A53, IMX_SC_PM_CLK_CPU);
imx_clk_scu("a72_clk", IMX_SC_R_A72, IMX_SC_PM_CLK_CPU);

/* LSIO SS */
imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER);

[igorpadykov · Accepted solution]

for kernel 5.4 one can look at third party example (IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT) :

https://github.com/toradex/device-trees/blob/toradex_5.4-2.1.x-imx/dts-arm64/imx8qxp-colibri.dtsi

https://developer.toradex.com/products/colibri-som-family/modules/colibri-imx8x#tab-software

Best regards
igor

[zhengguang_yang]

I tried this method and it didn't work

My modification is as follows:

imx8qxp.dtsi:

pwm2: pwm@5d020000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x5d020000 0x10000>;
clock-names = "ipg", "per";
clocks = <&pwm2_lpcg 4>,
<&pwm2_lpcg 1>;
assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
status = "disabled";
};

Add the following content to the DTS file of our board

pinctrl_pwm_d: pwmd {
fsl,pins = <
IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */
>;
};

&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_d>;
#pwm-cells = <2>;
};

[zhengguang_yang]

The test is normal after modifying the following contents:

reg = <0x0 0x5d020000 0 0x10000>;

Thank you very much