Working with both MII and RGMII on iMX6 Solo X

[alessandromaggi]

in our system we've connected an iMX6 Solo X to a Microchip KSZ8873FLLI switch using an MII interface at 100mbps.

For doing this, starting from the Sabre demo schematics, we've modified ENET1 connections to implement the MII physical layer.

ENET2 has been configured in RGMII mode and connected to a 100-FX PHY.

Actually, after the card power-on ENET2 is always working, while ENET1 sometimes is not.

Comparing TXD waveform to ENET2_TX_CLK, we've seen that the phase between data  and clock seems to change after each power-on.

Using SMI interface, we've verified that the KSZ8873 is always configured in a proper way.

Our main doubt is whether clock tree configuration is correct or not.

The clock tree is depicted in the attached block diagram.

ENET2_REF_CLK is used for providing the system clock to PHY and switch.

Referring to register IOMUXC_GPR_GPR1, our configuration is the following: 

ENET1_CLK_SEL = 0

ENET2_CLK_SEL = 0

ENET1_TX_CLK_DIR = 0

ENET2_TX_ CLK_DIR = 0

and IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK is set to ALT1.

Is this a correct setup for working with ENET1 in MII mode and ENET2 in RGMII mode?

[MichaelV]

alessandromaggi‌,

You said: "Using SMI interface, we've verified that the KSZ8873 is always configured in a proper way."

How did you convince the ENET module to issue a read with OP set to 00? Can you share the code you used to issue a read from the KSZ8873 using SMI?

What we see and understand from the iMX6 RMs, the ENET module always treats an operation with OP set to 00 as a write operation, but for an SMI read, OP needs to be 00. We can't seem to read any register from the KSZ8873 using SMI because of this ENET module restriction.

I'm super interested to see how you managed to convince the ENET module to do an SMI read.

I really hope you are willing to help us out here!

Many thanks in advance,

Michel.

[alessandromaggi]

Hi Michel,

(I'm not sure I understand your question properly since I am a very beginner on IMX architecture)

I added my own ioctl to the kernel driver (freescale/fec_main.c) and inside it I simply call a mdiobus_read.

Then, I created a very simple program to issue the ioctl on the interface connected to the KSZ8873, and get the response.

Nothing special as you see.

[alessandromaggi]

MichaelV‌ 

I understood the misunderstanding.

I said "Using SMI interface" while actually I meatn "Using MIIM interface"

[MichaelV]

alessandromaggi

That means you are only able to access the standard 16-bit PHY registers, and you are NOT able to access any of the internal 8-bit registers (global, port and advanced control registers, correct?

So, if you are not using SMI, how did you even configure the KSZ8873? Through a NAND tree?

Problem is that the iMX6 cannot generate a read with OP set to 00 (which is required for SMI). The iMX6 is able to generate a WRITE for SMI, just not a READ, or at least I haven't found a way yet.

So, when you said you were able to verify correct configuration of the KSZ8873 by verifying all register contents over SMI, I had some hope...

[alessandromaggi]

Michel,

Sorry I didn't mean to generate false hopes I confirm I can only access the 16 bits standard registers. I've tried hard to access the internal 8 bits but I couldn't manage. I'm only able to check standard registers and everything is fine there.

In my application I don't need a special configuration, so I didn't do anything special, hardware connection, select fixed-phy in dts and the switch was up and running.

BTW I solved my issue: it was related to an improprer clock initialization in the IMX registers

[art]

To make me able to accurately study the case, please provide the exact shematic of external connections of the ENET1 and ENET2 interfaces.

Best Regards,
Artur