Hello,
On the affected board, the Phy controller has been changed to mxl86110I.
There is a problem with the EQOS driver interrupt processing for Windows 10 IoT Enterprise with BSP 1.5.0.
There is no problem with 10M/100M connections.
Even with a 1G connection, communication itself is possible without any problems.
However, when you unplug the cable, an immediate interrupt occurs, Windows locks up, and eventually the system watchdog interrupt occurs, causing a reboot.
After investigating, we found that a MAC_INTERRUPT had occurred, and the EQOS ISR processing was set to not process anything other than DMA interrupts, as shown in the source code below.
As a result, the MAC_INTERRUPT interrupt is not cleared and continues to occur.
_Use_decl_annotations_
BOOLEAN EnetIsr(NDIS_HANDLE MiniportInterruptContext, PBOOLEAN QueueDefaultInterruptDpc, PULONG TargetProcessors)
{
PMP_ADAPTER pAdapter = (PMP_ADAPTER)MiniportInterruptContext;
UNREFERENCED_PARAMETER(TargetProcessors);
DBG_ENET_DEV_ISR_METHOD_BEG();
if (pAdapter->ENETRegBase->DMA_CH[0].DMA_CHX_INT_EN.R != 0U) {
pAdapter->ENETRegBase->DMA_CH[0].DMA_CHX_INT_EN.R = 0x00; // Disable all ENET interrupts. (EnetIsr will not be called again until interrupts are enabled in EnetDpc)
pAdapter->DpcQueued = TRUE; // Remember that EnetDpc is queued
*QueueDefaultInterruptDpc = TRUE; // Schedule EnetDpc on the current CPU to complete the operation
__analysis_assume(*TargetProcessors = 0); // If QueueDefaultInterruptDpc value is set to TRUE, NDIS ignores the value of the TargetProcessors parameter. Suppress analyser warning "Returning uninitialized memory".
} else {
*QueueDefaultInterruptDpc = FALSE; // Do not schedule Dpc
*TargetProcessors = 0;
DBG_ENET_DEV_ISR_PRINT_WARNING("Spurious Interrupt.");
}
DBG_ENET_DEV_ISR_METHOD_END();
return *QueueDefaultInterruptDpc;
}
The issue can be resolved by adding a process to the else side of the above if statement that clears the bit that is causing MAC_INTERRUPT.
What we don't understand is why MAC_INTERRUPT occurs.
In the following code for EnetQos_Init, MAC_INTERRUPT_ENABLE is set to 0.
// Disable all interrupts
pAdapter->ENETRegBase->DMA_CH[0].DMA_CHX_INT_EN.R = 0U;
pAdapter->ENETRegBase->MAC_INTERRUPT_ENABLE.R = 0U;
In the SoC reference manual (i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024), I confirmed that setting this to 0 disables interrupts.
Below are some questions.
1.Is this a typo in the SoC reference manual?
2.Is this a problem with the SoC's EQOS interrupt?
3.Is the process of disabling MAC_INTERRUPT insufficient?
In BSP1.5.1, we confirmed that five MASK registers are set to disable interrupts other than DMA.
Therefore, we have reflected the differences in the EQOS driver source from BSP1.5.0 to BSP1.5.1.
(We have confirmed that if the BSP1.5.1 fix is not applied, a similar phenomenon will occur when the communication load is high.)
Best regards.
Koji Okuda
