Why the PIXCLK frequency is not consistant ?

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

Why the PIXCLK frequency is not consistant ?

1,959 次查看
leejey
Contributor I

Hi,

I am using iMX51 connected a WVGA LCD.

I measured the PIXCLK frequency and it is a variant waveform. It means that the high time on the clock pulse varies in a scope. As we know that Pixel clock frequency is directly related with the frame refresh rate. But I don't know why?

标签 (1)
标记 (2)
0 项奖励
回复
2 回复数

1,561 次查看
leejey
Contributor I

Hi Florent Auger,

You supply me a great answer. Thanks a lot.

I will adjust the pixclk frequency for a better duty cycle.

0 项奖励
回复

1,561 次查看
FlorentAuger
Contributor V

Hello,

The typical structure for the IPU driver of Linux is the following.

struct fb_videomode {
const char *name;    /* optional */
u32 refresh;        /* this parameter is ignored */
u32 xres;        /* pixel */
u32 yres;        /* pixel */
u32 pixclock;        /* pico second */
u32 left_margin;    /* pix_clk */
u32 right_margin;    /* pix_clk */
u32 upper_margin;    /* line */
u32 lower_margin;    /* line */
u32 hsync_len;        /* pix_clk */
u32 vsync_len;        /* line */
u32 sync;
u32 vmode;
u32 flag;
};

 

The timing diagrams are the following:

___ <- hsync_len ->______________________________________
      |____________|                        <--- xres --->                         |________
                             <- left_margin -> _________ <- right_margin ->
______________________________|                 |_______________________


___ <- vsync_len -> ____________________________________________
     |_____________|                          <-------- yres ------>                          |____
                             <- upper_margin ->___   _..._    ___ <- lower_margin ->
________________________________|     |_|       |_|     |____________________

 

The period of the pixel clock is given in pico seconds. The dividers inside the IPU are not integer, and depending on the value of pixclock, the clock might have a duty cycle that is different from 50%.

The calculation for the dividers being made automatically by the driver, it is sometimes necessary to slightly adjust pixclock to a higher or lower value to get a nice clock.

0 项奖励
回复