Why nop is inserted in imx7d_low_power_idle.S?

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Why nop is inserted in imx7d_low_power_idle.S?

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Senior Contributor I

Hi community,

Our customer have a question about i.MX7S low power mode.
Please see line 698 of arch/arm/mach-imx/imx7d_low_power_idle.S in L4.1.15_1.0.0-ga.
There are 25 nops after wfi from this line.
Would you let me know the intent why there are these nops?


Best Regards,
Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

Hello,

  when exit low power mode, some delay is necessary to make sure signals

stable enough for DDR operation.

 

Have a great day,

Yuri

 

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NXP TechSupport
NXP TechSupport

Hello,

  when exit low power mode, some delay is necessary to make sure signals

stable enough for DDR operation.

 

Have a great day,

Yuri

 

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Note: If this post answers your question, please click the Correct

Answer button. Thank you!

------------------------------------------------------------------------------

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Senior Contributor I

Hi Yuri,

Thank you for your reply.

> when exit low power mode, some delay is necessary to make sure signals
> stable enough for DDR operation.

What is the factor to decide how long delay is needed?

Time to stabilize DDR clock from PLL?

Or DDR chip requires some delay?

Best Regards,

Satoshi Shimoda

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117 Views
NXP TechSupport
NXP TechSupport

Hello,

 when exit  low power mode, ~10us delay is necessary.

Regards,

Yuri.