Why imx6solo can not boot from nand flash?

翔李 · ‎07-17-2017

HI,

My board can not boot from 256MB nand flash when power on,and nand flash can run when boot from TF cards then manual command to run nand falsh.It looks like that the boot mode is somewhere wrong.The nand is W29N02GVSIAA.The following picture is my sch. and NC means not stuff.

The "NANDF_CS2" connects to TF card socket's CD pin to detect card insert,when insert TFcard,it boot from TF,when not insert TF card,it boot from nand flash.

igorpadykov · ‎07-17-2017

Hi 翔李

what is full processor name used in the case ?

Best regards
igor

翔李 · ‎07-18-2017

the part number is MCIMX6S6AVM08AC,the picture is following. also show the log of boot information from TF and tf manual command nand run.

1. Using SPL booting from TF card:

U-Boot SPL 2017.07-rc3-00016-g913243e (Jul 18 2017 - 14:57:51)

DDR: 512 MiB

Booting from MMC

Trying to boot from MMC1

reading zImage-icar2.dtb

reading zImage

Booting Linux on physical CPU 0x0

Linux version 4.1.15 (gcc version 5.3.0 (GCC) ) #72 SMP PREEMPT Tue 7

CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d

CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

Machine model: Freescale i.MX6 DualLite SABRE Smart Device Board

Reserved memory: created CMA memory pool at 0x28000000, size 128 MiB

Reserved memory: initialized node linux,cma, compatible id shared-dma-pool

Memory policy: Data cache writeback

CPU: All CPU(s) started in SVC mode.

PERCPU: Embedded 10 pages/cpu @d7b8b000 s11660 r8192 d21108 u40960

Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048

Kernel command line: console=ttymxc3,115200 root=/dev/mmcblk2p2 rootwait

rw video=mxcfb0:dev=adv7392

PID hash table entries: 2048 (order: 1, 8192 bytes)

Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)

Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)

Memory: 382276K/524288K available (3930K kernel code, 169K rwdata, 1412K

rodata, 224K init, 188K bs)

Virtual kernel memory layout:

vector : 0xffff0000 - 0xffff1000 ( 4 kB)

fixmap : 0xffc00000 - 0xfff00000 (3072 kB)

vmalloc : 0xe0800000 - 0xff000000 ( 488 MB)

lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)

modules : 0xbf000000 - 0xc0000000 ( 16 MB)

.text : 0xc0008000 - 0xc053fc88 (5344 kB)

.init : 0xc0540000 - 0xc0578000 ( 224 kB)

.data : 0xc0578000 - 0xc05a2480 ( 170 kB)

.bss : 0xc05a5000 - 0xc05d43bc ( 189 kB)

SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1

Preemptible hierarchical RCU implementation.

Additional per-CPU info printed with stalls.

RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.

RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2

NR_IRQS:16 nr_irqs:16 16

L2C-310 erratum 769419 enabled

L2C-310 enabling early BRESP for Cortex-A9

L2C-310 full line of zeros enabled for Cortex-A9

L2C-310 ID prefetch enabled, offset 16 lines

L2C-310 dynamic clock gating enabled, standby mode enabled

L2C-310 cache controller enabled, 16 ways, 512 kB

L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76050001

...

nand: device found, Manufacturer ID: 0xef, Chip ID: 0xda

nand: Winbond W29N02GV

nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64

gpmi-nand 112000.gpmi-nand: mode:4 ,failed in set feature.

Bad block table found at page 131008, version 0x01

Bad block table found at page 130944, version 0x01

nand_read_bbt: bad block at 0x0000016c0000

nand_read_bbt: bad block at 0x000001be0000

gpmi-nand 112000.gpmi-nand: driver registered.

CAN device driver interface

2. Using bmode to booting SPL from nand flash

U-Boot 2016.03-00268-gbaa41de-dirty (Jul 17 2017 - 16:30:27 +0800)

CPU: Freescale i.MX6SOLO rev1.2 at 792MHz

CPU: Automotive temperature grade (-40C to 125C) at 57C

Reset cause: POR

NAND: 256 MiB

MMC: FSL_SDHC: 0

Normal Boot

Hit any key to stop autoboot: 0

=>

=> bmode nand

resetting ...

U-Boot SPL 2017.07-rc3-00016-g913243e (Jul 18 2017 - 14:57:51)

DDR: 512 MiB

Booting from MMC

Trying to boot from MMC1

reading zImage-icar2.dtb

reading zImage

Booting Linux on physical CPU 0x0

Linux version 4.1.15 (gcc version 5.3.0 (GCC) ) #72 SMP PREEMPT Tue 7

CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d

CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

Machine model: Freescale i.MX6 DualLite SABRE Smart Device Board

Reserved memory: created CMA memory pool at 0x28000000, size 128 MiB

Reserved memory: initialized node linux,cma, compatible id shared-dma-pool

Memory policy: Data cache writeback

CPU: All CPU(s) started in SVC mode.

PERCPU: Embedded 10 pages/cpu @d7b8b000 s11660 r8192 d21108 u40960

Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048

Kernel command line: console=ttymxc3,115200 root=/dev/mmcblk2p2 rootwait

rw video=mxcfb0:dev=adv7392

PID hash table entries: 2048 (order: 1, 8192 bytes)

Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)

Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)

Memory: 382276K/524288K available (3930K kernel code, 169K rwdata, 1412K

rodata, 224K init, 188K bs)

Virtual kernel memory layout:

vector : 0xffff0000 - 0xffff1000 ( 4 kB)

fixmap : 0xffc00000 - 0xfff00000 (3072 kB)

vmalloc : 0xe0800000 - 0xff000000 ( 488 MB)

lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)

modules : 0xbf000000 - 0xc0000000 ( 16 MB)

.text : 0xc0008000 - 0xc053fc88 (5344 kB)

.init : 0xc0540000 - 0xc0578000 ( 224 kB)

.data : 0xc0578000 - 0xc05a2480 ( 170 kB)

.bss : 0xc05a5000 - 0xc05d43bc ( 189 kB)

SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1

Preemptible hierarchical RCU implementation.

Additional per-CPU info printed with stalls.

RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.

RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2

NR_IRQS:16 nr_irqs:16 16

L2C-310 erratum 769419 enabled

L2C-310 enabling early BRESP for Cortex-A9

L2C-310 full line of zeros enabled for Cortex-A9

L2C-310 ID prefetch enabled, offset 16 lines

L2C-310 dynamic clock gating enabled, standby mode enabled

L2C-310 cache controller enabled, 16 ways, 512 kB

L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76050001

...

nand: device found, Manufacturer ID: 0xef, Chip ID: 0xda

nand: Winbond W29N02GV

nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64

gpmi-nand 112000.gpmi-nand: mode:4 ,failed in set feature.

Bad block table found at page 131008, version 0x01

Bad block table found at page 130944, version 0x01

nand_read_bbt: bad block at 0x0000016c0000

nand_read_bbt: bad block at 0x000001be0000

gpmi-nand 112000.gpmi-nand: driver registered.

igorpadykov · ‎07-18-2017

hi

please refer to sect.8.5.2.8 IOMUX Configuration for NAND i.MX6SDL Reference Manual
http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SDLRM.pdf

NAND boot is only supported on chip select 0.

general steps for debugging nand boot are given in

https://community.freescale.com/thread/307723

igor

翔李 · ‎07-18-2017

HI,

I already connect nand's ce# to NANDF_CS0 of imx6solo,it is ok.

So,I still do not find the problem.

igorpadykov · ‎07-18-2017

Hi

please try to program nand using mfg tools found on link

i.MX 6 / i.MX 7 Series Software and Development Tool|NXP

use mfgtool2-yocto-mx-sabresd-nand.vbs script

~igor

翔李 · ‎07-19-2017

When I pull down the cfg1_4 from 1 to 0,my board can auto boot from nand flash.why?

and how do cfg2_4 effect nand boot?

igorpadykov · ‎07-19-2017

cfg1_4 controls pad settings (affect drive strength and associated with them

signal integrity) defined in Table 5-7. NAND Boot Fusemap i.MX6SDL Reference Manual.

翔李 · ‎07-19-2017

Thanks.

Now I can boot from nand flash when power up,imx6solo can read out the MFR ID and Device ID,but then fail to read ONFI ID(the read result is same as the MFR ID and device ID).why?My nand flash is W29N02GVSIAA.

can you give me the demo software of nand flash?

Log of boot information is following.

IVICAR Release Distro 4.1.15-2.0.3 icar2 /dev/ttymxc3

icar2 login:

U-Boot SPL 2017.07-rc3-00015-g4c367f6-dirty (Jul 20 2017 - 14:16:30)

DDR: 512 MiB

Booting from NAND

Trying to boot from NAND

spl: nand - using hw ecc

cmdfunc: NAND_CMD_READID 0x00

id_data[0]: 0xef

id_data[1]: 0xda

id_data[2]: 0x90

id_data[3]: 0x95

id_data[4]: 0x4

id_data[5]: 0x0

id_data[6]: 0x0

id_data[7]: 0x0

cmdfunc: NAND_CMD_READID 0x20

id_data[0]: 0xef

id_data[1]: 0xda

id_data[2]: 0x90

id_data[3]: 0x95

NOT ONFI FLASH

Failed to identify

andreascian · ‎01-29-2019

Is a u-boot SPL fault. There's a NAND protocol violation in mxs_nand_command() which lead to failure on some NAND devices (like Winbond one) but that still works on some other devices (e.g. Spansion one) that seems to answer anyway.

Here is a patch that solve this issue as can be applied on current u-boot master (this is the patch I've sent mainline)

From d6227c8badce7ce4fa2aad0976a916a6c09c6b1f Mon Sep 17 00:00:00 2001
From: Andrea Scian <andrea.scian@dave.eu>
Date: Tue, 29 Jan 2019 11:30:12 +0100
Subject: [PATCH 1/2] mtd: mxs_nand_spl: fix nand_command protocol violation

mxs_nand_command() implementation assume that it's working with a
LP NAND, which is a common case nowadays and thus uses two bytes
for column address.

However this is wrong for NAND_CMD_READID and NAND_CMD_PARAM, which
expects only one byte of column address, even for LP NANDs.
This leads to ONFI detection problem with some NAND manufacturer (like
Winbond) but not with others (like Samsung and Spansion)

We fix this with a simple workaround to avoid the 2nd byte column address
for those two commands.

Also align the code with nand_base to support 16 bit devices.

Tested on an iMX6SX device with:
* Winbond W29N04GVSIAA
* Spansion S34ML04G100TF100
* Samsung K9F4G08U00

Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
CC: Stefano Babic <sbabic@denx.de>
---
 drivers/mtd/nand/raw/mxs_nand_spl.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c
index 2d7bbe83cc..ad3b7ade64 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -22,8 +22,20 @@ static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
 
        /* Serially input address */
        if (column != -1) {
+               /* Adjust columns for 16 bit buswidth */
+               if (chip->options & NAND_BUSWIDTH_16 &&
+                               !nand_opcode_8bits(command))
+                       column >>= 1;
                chip->cmd_ctrl(mtd, column, NAND_ALE);
-               chip->cmd_ctrl(mtd, column >> 8, NAND_ALE);
+
+               /*
+                * Assume LP NAND here, so use two bytes column address
+                * but not for CMD_READID and CMD_PARAM, which require
+                * only one byte column address
+                */
+               if (command != NAND_CMD_READID &&
+                       command != NAND_CMD_PARAM)
+                       chip->cmd_ctrl(mtd, column >> 8, NAND_ALE);
        }
        if (page_addr != -1) {
                chip->cmd_ctrl(mtd, page_addr, NAND_ALE);
-- 
2.19.2
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igorpadykov · ‎07-20-2017

please check Demo Images for sabre ai board, it supports nand.

http://www.nxp.com/webapp/Download?colCode=IMX6_N7.1.1_1.0.0_ANDROID_DEMO_AI_BSP&appType=license&loc...

Best regards
igor

Why imx6solo can not boot from nand flash?

Why imx6solo can not boot from nand flash?

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