Why does GPT2 timer run sometimes faster and sometimes slower in MCIMX6Y2CVM08AB?

[zlk1214]

Environment: uboot2016.03 + linux kernel 4.1.15 + busybox rootfs.

Kenrel module 1: gpt_timer
When this module is inserted by using insmod command, the GPT2 timer is configured and started.
The GPT2 clock input is configured as ipg_clk:
In CCM_CCGR, CG12(gpt2_bus_clk_enable) is set to 3.
GPT2_OCR1 is set to 19999.
GPT2_PR is set to 3299.
In GPT2_CR, CLKsrc=01(ipg_clk,66MHz), EN=1.
The expected overflow frequency is 66MHz/(19999+1)/(3299+1)=1Hz.
When this module is removed by using rmmod command, the GPT2 timer is stopped by resetting GPT2_CR_EN.
Kernel module 2: segdisp_driver
There's a 7-segment display with 8 digits which is drived by two 74HC595 chips.
This module sets which digit to be on, and what number to be displayed.

Userspace app: segdisp_app
This app has an infinite loop. In the loop, the GPT2 current counter value is read from gpt_timer module. Then the 8 digits of the 7-segment display is scanned once to display the number.
When this app is running, the 7-segment display is continuously scanned.
When this app is killed by Ctrl+C, the 7-segment display is not scanned.

Insert gpt_timer and segdisp_driver modules. Start segdisp_app.
It's suprising that the GPT2 overflow frequency is 3 times slower than expected, approximately 24MHz, when the segdisp_app is running (scanning the 7-segment display with no delay).
When the segdisp_app is not running, the 7-segment display is not scanned. The GPT2 overflow frequency is much slower! Approximately 10 times slower --> 2.4MHz.
After restarting segdisp_app, GPT2 resumed to run in approximately 24MHz frequency.

[ 4735.694601] CCM->CCGR0=0xcfc03f0f
[ 4735.697943] CCM->CCGR1=0x3fff0030
[ 4735.701263] GPT2->CR=0x00000000
[ 4735.706800] GPT2->IR=0x01
[ 4735.709446] GPT2->SR=0x00
[ 4735.731338] gpt2 irq number=213
[ 4735.736296] GPT2->CR=0x00000041

[ 4796.616176] CCM_CBCDR=0x00018d00
[ 4796.619431] [IPG_PODF]=1 (divide by 2)
[ 4796.625408] [AHB_PODF]=3 (divide by 4)
[ 4796.629358] [GLITCHLESS MUX]=[PERIPH_CLK_SEL]|[PLL_BYPASS_EN2]=0|0=0
[ 4796.637781] CCM_CBCMR=0x25228324
[ 4796.641844] [PRE_PERIPH_CLK_SEL]=0
[ 4796.646642] CCM_CSCMR1=0x14902140
[ 4796.649984] [PERCLK_PODF]=0 (divide by 1)
[ 4796.655812] CCM_CMEOR=0x7fffffff
[ 4796.659065] [MOD_EN_OV_GPT]=1

Accroding to the manual, GPT2 clock input path is:
(pre_periph_clk_sel=0)PLL2(528MHz) -> GLITCHLESS MUX(=0) -> ahb_podf divider=4 -> ipg_podf divider=2 -> IPG_CLK_ROOT -> PERCLK_PODF divider=1 -> PERIPH_CLK_ROOT
IPG_CLK_ROOT=528MHz/4/2=66MHz
PERIPH_CLK_ROOT=66MHz/1=66MHz

The frequency of PLL2 is not programmable. Why is the output frequency to GPT2 is variant?