Which signal is the clock source for i.MX6's ENET_MDC?

[Ryo_Aoki]

Hi NXP.

We are currently having a problem with i.MX6solo's ENET_MDC and are gathering information to resolve it.
Which signal is the clock source for i.MX6solo's ENET_MDC?
I checked the reference manual and can't find any information.
It would be nice if there was documentation showing the connection with PLL.

Best regards.

[Zhiming_Liu · Accepted solution]

Hi @Ryo_Aoki 

It's from enet module clock: ipg_clk, the name in device tree is IMX6SX_CLK_ENET.

It would be nice if there was documentation showing the connection with PLL.

-->I couldn't find such connection diagram

Best Regards

Zhiming

[Ryo_Aoki]

Hi Zhiming.

Thank you for your reply.
However, I am targeting i.MX6solo, not i.MX6SX.
Is the clock source ipg_clk for i.MX6solo as well?

And can the clock source to this ENET_MDC be a different clock source than ipg_clk?
I was assuming that PLL6, for example, was being used.

Best regards.