Which serial interface is suitable for my protocol (i.MX8 ULP)?

[paullegart]

My processor is i.MX8 ULP.

I've got a chip which has a master SSI interface like that:

There are 3 lines in the interface: clock (CLK), serial data (DATA) and FrameSync (FS). Each frame contains three words of 16 bits each. FS is active on the last bit of the frame. Data is streaming (no gaps).

So which interface should I use to reiceive data from this chip? It actually doesn't matter which core should manage the signal but A35 is preferrable.

As I guess I2S is not suitable because it can manage 2 channels only. Regarding SPI interface I have no idea how to set it up for streaming (no gaps) mode.

[JorgeCas]

Hello,

I think it should be almost the same situation with SAI or SPI interfaces since you need to create a new driver to support that device in your design.

Which IC do you want to interface? Maybe there is something that could be used as reference in our side.

Best regards.

[paullegart]

The chip is AD9874. The topic is just more about hardware support of this interface rather the driver but I would glad to hear any suggestions about everything.