Where pll4_bypass_src is set to choose osc 24MHz or CLK2_N/P as source in linux BSP code?

[gelei]

Hi NXP engineers,

On the 6qp_sabreauto board, ESAI use 24.576Mhz external osc as clock source,and the clock route is like this:

In the kernel code, only esai_sel is set by imx6qdl_sabreauto.dtsi to choose 'PLL4 divide clock':

I didn't see where pll4_bypass_src is set in the BSP code:

We need to use 24MHz osc as pll4 source，so we need to know where pll4_bypass_src is set in the BSP code(but we can't find related code).

Can someone explain this in detail? LilyZhang‌ liqiang‌

Thanks! 

[igorpadykov]

thanks, pll4_bypass_src is set in the BSP code in linux/arch/arm/mach-imx/clk-imx6q.c :

    clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1,
pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); 

Best regards
igor

[gelei]

Hi igor,

the esai clk route for sabreauto board is as below:

[gelei]

Ignore this topic. I know how imx6 sabreauto board handle  pll4_bypass_src now.