Where is the start address of System Debug SJC memory map of i.MX53?

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Where is the start address of System Debug SJC memory map of i.MX53?

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m_c
Senior Contributor I

Where is the start address of System Debug SJC memory map of i.MX53?

According to the document, it said 0x0h. But it should be belong to boot rom.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   Using Extradebug Registers is special Freescale (NXP) JTAG-based technology, used mainly
for internal (manufacturer)  testing. It requires general JTAG interface,
that usually is used for BSDL
testing.
Please refer to section 67.10 (Programmable Registers)
of the RM : “SJC registers are only
accessible by JTAG interface. They are not memory mapped
to processor address space, so the absolute
addresses provided by default in the SJC memory map
are not valid.”


Have a great day,
Yuri

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m_c
Senior Contributor I

We have ARM DS-5 and can connect with MCIMX53-QSB. May we get SJC_SSR via ARM DS-5?

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