Where is MR3/ZQ calibration set up for mx6sl in u-boot or kernel?

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Where is MR3/ZQ calibration set up for mx6sl in u-boot or kernel?

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jayakumar2
Contributor V

Hi,

This is related to the previous post I made about ZQPAD and ZQ resistor values. Selecting ZQPAD and ZQ resistor value for i.mx6SL and LPDDR2 

We're using a custom board with i.mx6sl ( MCIMX6L8DVN10AB ) and EDB8132B4PM-1D-F-D LPDDR2 memory. I found that by changing drive strength settings in GRP_B0DS and others, I'm able to make boards that were previously failing, now pass. However, I still see upper addresses failing. I'm suspicious whether ZQ calibration is being run and also whether the MR3 setting is done for both chipselects on the LPDDR2 memory.

I am wondering where is ZQ calibration done and where does the MR3 register get set (for setting resistance of LPDDR2 DQ driver)? ie: which code function does it.

I found some code in arch/arm/cpu/armv7/mx6/ddr.c :

/* Step 7: Enable MMDC with desired chip select */
mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */

/* Step 8: Write Mode Registers to Init LPDDR2 devices */
for (cs = 0; cs < sysinfo->ncs; cs++) {
/* MR63: reset */
mmdc0->mdscr = MR(63, 0, 3, cs);
/* MR10: calibration,
* 0xff is calibration command after intilization.
*/
val = 0xA | (0xff << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* MR1 */
val = 0x1 | (0x82 << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* MR2 */
val = 0x2 | (0x04 << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
/* MR3 */
val = 0x3 | (0x02 << 8);
mmdc0->mdscr = MR(val, 0, 3, cs);
}

but I now believe that code does not get run. Even if u-boot is setup for SPL, it does not seem to be sufficient to set CONFIG_SPL=y as that code still does not seem to get reached.

Do you know where ZQ calib and MR3 is done for u-boot on 6sl? Should it be done in u-boot? Or is it in kernel and if it is done in kernel on 6sl, where is it being done? It seems critical to memory stability but not well documented.

Thanks!

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jaya

these codes, invoked from mx6_dram_cfg() are used only for uboot "spl" option

http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale/mx6slevk/mx6slevk.c?h=i... 

Such option has ability to perform calibration in uboot, any issues with it can be posted on uboot mail list:

U-Boot Info Page 

NXP uboot does not use spl and use separate ddr tool calibration utility on

i.MX6/7 DDR Stress Test Tool V2.70 

Calibration coefficients found using that tool can be placed in uboot imximage.cfg file

uboot-imx.git - Freescale i.MX u-boot Tree 

Best regards
igor
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jayakumar2
Contributor V

Hi Igor,

Thanks for your reply.

Yes, as I mentioned mx6_dram_cfg() [ that's the code I pasted above ] is never called, even if CONFIG_SPL=y is enabled. It seems non-trivial to get mx6_dram_cfg to get called since board_init_f() is also not called just by doing CONFIG_SPL=y.

Setting the calibration coefficients for DQS in imximage.cfg will only setup the drive strength for the SoC side. That means nothing sets up the MR3 (matching resistance of LPDDR2 DQ drive). It needs to be setup for each chipselect of the LPDDR2 like how it is done in mx6_dram_cfg(). That's the part I pasted (key line below):

for (cs = 0; cs < sysinfo->ncs; cs++) {

...

If I understand you correctly, then by default (since SPL is not enabled in u-boot and doesn't seem trivial to setup), then the MR3 register on DDR is never setup by u-boot or the kernel. That would mean that by default on 6sl boards, if the estimated trace resistance is other than the default 40 Ohm, then there can be problems with memory (which is what I'm seeing with bitflip errorrs) and even if one changes the SoC calibration coefficients to the correct value, then the LPDDR2 side will be wrong. Is that correct? 

Thanks!

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jaya

>Setting the calibration coefficients for DQS in imximage.cfg will only setup the drive strength for the SoC side. 

right, ZQ calibration for DDR I/O pads is used for calibrating the DDR driving strength.

>If I understand you correctly, then by default (since SPL is not enabled in u-boot and doesn't seem trivial to setup), then the >MR3 register on DDR is never setup by u-boot or the kernel. That would mean that by default on 6sl boards, if the >estimated trace resistance is other than the default 40 Ohm, then there can be problems with memory (which is what I'm >seeing with bitflip errorrs) and even if one changes the SoC calibration coefficients to the correct value, then the LPDDR2 >side will be wrong. Is that correct? 

correct

Best regards
igor

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jayakumar2
Contributor V

Hi Igor,

Thanks for your reply.

>> MR3 register on DDR is never setup by u-boot or the kernel

> correct

That's a big problem right? This means that anyone who has boards where the DDR traces deviate from the 40 Ohm value will experience sporadic and random memory corruption.

Thanks,

jaya

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igorpadykov
NXP TechSupport
NXP TechSupport

one needs to follow routing rules defined in i.MX6 User Guide

https://cache.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf 

if necessary these settings can be added to imximage.cfg 

~igor

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jayakumar2
Contributor V

Hi Igor,

> one needs to follow routing rules defined in i.MX6 User Guide

Yes, I understand that. But as can be seen, there are sometimes issues with manufacturing that result in problems where not all boards have trace impedance that is within those constraints.

> if necessary these settings can be added to imximage.cfg 

I'm confused by this statement. Do you mean the MR3 register in LPDDR2 can be set through imximage.cfg? 

Thanks!

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jaya

yes, please check script exampe in ddr test tool v.2.70 (folder /script/mx6sl/MX6SL_EVK_LPDDR2_512MB_32bit.inc)
https://community.nxp.com/docs/DOC-105652 

Best regards
igor

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