Hello,
We are working with the iMX8ULP and have problems reading in the BOOT MODE pins in certain HW configurations.
The reset0_b signal is defined by the POR_B signal of the PMIC and has a pullup to buck1
The reset1_b signal also has a pullup to buck1.
VDD_PTA and the BOOT_Mode pads receive voltages from LDO2.
How must the signals to reset0 and reset1 arrive so that the 8ULP can safely read the Boot MODE pins? From BOOT_MODE0 and BOOT_MODE1 as well as from the BTx_CFGx pins?
In our setup, we can assign the reset0 and reset1 signals to a button. When the board is powered up and after a certain time X reset0 is briefly pulled to ground, then a reset is performed and the boot mode pins can be successfully read.
Alternatively, if reset1 is pulled to ground when power is applied and is released after an arbitrary time X, then the boot mode pins will also be read.
So what is the clear definition of how the reset signals must be executed?
