What state shall the data and clock lines be when MIPI-CSI DPHY is resetting?

[dehuanxin]

According to IMX6QRM <40.3.1 Startup Sequence>:

Before DPHY reset all TX lanes must be in LP11 state (stop state).

I tried to verify this by probing into the ov5640_mipi driver.

However I printed the DPHY status in "ov5640_mipi.c" before and after "mipi_csi2_reset(mipi_csi2_info);" call in "ov5640_init_mode()" function and the status is 0x200, which means neither the clock lane nor the two data lane are in stop state.

If I understand correctly, the indicator for clock lane being in stop state is status 0x6xx, and the indicator for two data lanes being in stop state is 0xx30.

My question is:

1) what state should the clock lane be when the DPHY is resetting? HS DDR clock, LP00, or LP11?

2) what state should the data lanes be when the DPHY is resetting?

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I'm asking this because I have another FPGA front end that is connected to the MIPI-CSI2 camera port of a IMX6Q board and I can not get DPHY state to 0x3xx (which means DDR clock is not received).

This FPGA uses 1 data lane.

I tell the FPGA to set both clock and data to LP11 before I tell IMX6 to reset DPHY.

The DPHY status I get immediately after DPHY reset is 0x610. (clock lane is in stop state, clock lane is not in ULPS, data lane 1 is in stop state).

Then I tell FPGA to output DDR clock. Then DPHY state changes to 0x210 (clock lane is not in stop state, but is not receiving DDR clock, either, data lane 1 is in stop state).

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I probed the DDR clock on a oscilloscope and it looks normal: both CLK_P and CLK_N are about 200mV P-P with +300mV offset, which is within the spec according to IMX6Q datasheet.

So I think it's reasonable to believe that it's not a electrical/hardware problem, although both data and clock lanes go though a 20cm flex PCB cable.

I can not verify the slew rate because of the bandwidth of the scope (DDR clock is 160MHz and my scope is 200Mhz, so I lost almost all the harmonics).

The DPHY clock setting I use for the FPGA is 0x48(300-330MHz, 330MHz). I also tried different values and it doesn't help.

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I've been working on this for almost 2 weeks and this is as far as I can get.

What am I missing?

Any suggestions?

[igorpadykov]

Hi Dehuan

HS data transfer sequence should start as : LP-11,LP-01,LP-00,HS-0,Sync Sequence, then Payload Data.

The receiver side will enter high speed mode following the sequence of low-power

states in the lines: LP-11, LP-01, and LP-00. This sequence is seen as a high speed

mode request, and toggles the enabling oh the high speed receivers. The synchronization

is then achieved through the identification of the leader sequence in the received

differential high-speed data. Once synchronization is achieved, the PHY outputs

the received bytes trough the protocol layer, until a stop state (LP-11) is detected in the lane.

Best regards

igor

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[dehuanxin]

Hi, igor,

Thank you for your reply to every one of my questions and you've helped me get me closer and closer to a solution.

I understand the HS data initiation sequence, but from the DPHY Specification 1.0 I found out HS clock also has a initiation sequence: LP-11,LP-01,LP-00,HS-0, HS-clock.

Since my FPGA MIPI-CSI2 transmitter is not following this protocol when it starts transmitting clock, I'm wondering if this is the reason why IMX6Q receiver DPHY fails to receive the MIPI-CSI clock.

If that is the case then I need to contact the FPGA person to implement that HS clock initiation sequence.

Dehuan

[dehuanxin]

I think I might have found the problem.

The FPGA is not following the HS clock initiation procedure (MIPI DPHY Spec 1.0 Table 11, Line 935, Section 5.7).

On the scope I see it jumps to HS0/HS1 oscillation directly from LP11 and does not have HS-Req(LP01), Bridge(LP00) and HS0/Tclk-zero states at all.

Is it the case that the slave side DPHY on the IMX6Q won't enter status 0x3xx without proper HS clock initiation sequence? Or it's the opposite: even if the HS clock jumps from LP11 to HS clock, the slave DPHY can still enter 0x3xx?