Hello,
The parameter tCL of the i.MX6 Reference Manual really is CAS Latency, defined as the
delay, in clock cycles, between the internal Read command and the availability of the first
bit of output data. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL);
RL = AL + CL.
The CAS latency is programmable value. It may be recommended to leave its value without changing,
as in the (Excel) tool suggested. Note, tCL may depend on DDR frequency and the same value must be
used in i.MX6 MMDC and DRAM part (in Mode Register MR0).
From DRAM Datasheet, Table 2 (Speed Grade Information), recommended CL is 11 clocks for 800 MHz
memory device, meaning 13.75 ns; for 400 MHz, 13.75 ns is 6 clocks.
In the (Excel) table, 7 is taken for assurance.
Have a great day,
Yuri
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