What is the maximum counter clock of i.MX8M Mini PWM?

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What is the maximum counter clock of i.MX8M Mini PWM?

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m_c
Senior Contributor I

According to the below data. Is it mean the maximum counter clock is 1000MHz?

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi Mike,

Sorry for late reply, this is the update from our expert.

  Although there are following  source options  for PWM, we need to make sure the PWM clock is less than 66MHz, it is decided in soc backend implemenation;

 

  .clk_in                 /* [  7:  0]/ ( { |                           / [      7]    /   video_pll_clk                            , |                           / [      6]    /   system_pll1_80m_clk                      , |                           / [      5]    /   ext_clk_1                                , |                           / [      4]    /   system_pll3_clk                          , |                           / [      3]    /   system_pll1_40m_clk                      , |                           / [      2]    /   system_pll1_160m_clk                     , |                           / [      1]    /   system_pll2_100m_clk                     , |                           / [      0]    */   osc_25m_clk                              }

Hope this will do help for you.

Have a nice day

Rita

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi Mike,

Sorry for late reply, this is the update from our expert.

  Although there are following  source options  for PWM, we need to make sure the PWM clock is less than 66MHz, it is decided in soc backend implemenation;

 

  .clk_in                 /* [  7:  0]/ ( { |                           / [      7]    /   video_pll_clk                            , |                           / [      6]    /   system_pll1_80m_clk                      , |                           / [      5]    /   ext_clk_1                                , |                           / [      4]    /   system_pll3_clk                          , |                           / [      3]    /   system_pll1_40m_clk                      , |                           / [      2]    /   system_pll1_160m_clk                     , |                           / [      1]    /   system_pll2_100m_clk                     , |                           / [      0]    */   osc_25m_clk                              }

Hope this will do help for you.

Have a nice day

Rita

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi Mike,

The maximum counter clock can not achieve the 1000MHz, but the maximum value I am confirming it with our expert team, and when I get the update I will let you know.

Have a nice day

Rita

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