We are currently looking at the iMX6UL processor specifications to see if it suits our application. One of our constraints concerns the maximum bit rate of SAI devices in slave mode (SAI_BCLK). In the processor datasheet the minimum period of this signal is 4 x tsys (see S11 in Table 73 on page 85) but tsys is not specified. Can you tell me the value of this time?
For the KL28Zxxx processors the minimum period of this signal is 80 ns. Can we assume that the iMX6UL has the same specifications?
Hello,
SAI IP of i.MX6UL and i.MX6SX is the same, therefore You may refer to
i.MX6SX Datasheet(s).
http://www.nxp.com/assets/documents/data/en/data-sheets/IMX6SXCEC.pdf
In particular, according to Table 79 (Slave Mode SAI Timing) :
parameter S11 (SAI_BCLK cycle time (input)) is 20 ns as min.
Have a great day,
Yuri
------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct
Answer button. Thank you!