What is the issue ?? after resetting the Ethernet is not getting connected

[basklaranpriya]

I am using custom i.MX6 Quad, Porting Android Nougat , In that flavour Ethernet controller is not getting work.

Having error with Libphy, I Have read some threads and made the some reset changes in fec_MAIN.C , but nothing happening , getting same blog,

Could you suggest Why this happening, If any solution it would be helpful for me. I am stuck in this.

Error blog:

[   71.048004] fec 2188000.ethernet eth0: no PHY, assuming direct connection to switch
[   71.056388] libphy: PHY fixed-0:00 not found
[   71.060714] fec 2188000.ethernet eth0: could not attach to PHY

Thanks in Advance

[sameerarvikar]

I was facing same issue in imx6 ,and adding mdelay works fine

What GPIO pins u set inccorrectly,

Cause for u-boot , i added delay here

mdelay(100);
phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR), PHY_INTERFACE_MODE_RGMII);

The delay worked.

[jerrylain]

Hi, sameerarvikar

We modified ENET reference clock pin MUX_PAD_CTRL. You can double check it.

BTW, which version of u-boot you use. I found in uboot 2016, some phy related code might impact timing issue.

In drivers/net/phy/phy.c

/* Reset the bus */
if (bus->reset) {
bus->reset(bus);

/* Wait 15ms to make sure the PHY has come out of hard reset */
udelay(15000);
}

In older version of u-boot, here will always have a 15ms delay. But it 2016 u-boot, here won't have a delay if you didn't implement mii reset function. One of our project cannot get phy device without this delay. It need to add delay by myself to follow PHY spec.

Hope above information might help.

[joe_flowers]

Hi Jerry,

Can you give more details on this, please?

"We modified ENET reference clock pin MUX_PAD_CTRL. You can double check it."

Thank you!

[jerrylain]

Hi Joseph,

You should have a structure which like this

iomux_v3_cfg_t const enet_pads[] = {}

It has every GPIO pin's iomux setting to ethernet. MUX_PAD_CTRL is a macro can use here to set each pin's detail setting. Ex: pull up, pull down, SRE...etc. Just make sure every pins you need to use are included here and setting is correct.

[jerrylain · Accepted solution]

Not sure if it can help, previous I met similar problem but in Yocto.

It because PHY has problem, cannot get PHY status.

First, I tried to add delay when fec probe to wait PHY ready.

fec_main.c

// delay 100ms to wait phy ready
mdelay(100);

ret = fec_enet_mii_init(pdev);

Actually, it worked after add delay. But finally I found it because I set incorrect GPIO pins in u-boot, so ethernet does not initial correctly at u-boot, then kernel cannot get PHY status.

Hope it might help!