I would like to know the maximum achievable MIPI-CSI2 bandwidth with 4 lanes configuration for imx6 quad processor ?
I'm using 4 lanes MIPI configuration and able to achieve up to 750Mbps per lane, but imx6 guide mentioned 800Mbps per lane.
IMX6DQRM.pdf, page no 450.
One MIPI/CSI-2 port- IPU receives two components per cycle from the MIPI_CSI2
interface. The maximum bandwidth of the interface is as follows:
• 400MByte/sec for four data lanes configuration (800Mbps/lane)
• 375MByte/sec for 3 data lanes configuration (1000Mbps/lane)
• 250MByte/sec for 2 data lanes configuration (1000Mbps/lane)
• 125Mbyte/sec for 1 data lanes configuration (1000Mbps/lane)
So what is practically achievable MIPI-CSI2 bandwidth for 4 lanes ?
Thanks for your support.
Thanks Joan for your support.
Yes I have configured the clock correctly as per the attached (in your post) doc.
I could see the corruption in the image when I stream at 800Mbps.
What could be the problem ?
Any custom had tried with this configuration and able to achieve 800Mbps for 4 lanes configuration ?
Can you please check with dev team on this ?
Its kind of urgent for us. Could you please support us ?
PS: More over I'm able to stream the MIPI data 100Mbps/lane for 1 to 3 lanes, able to achieve total 3Gbps in 3lanes config. (as mentioned in RM)
Also getting total 3Gbps for 4 lanes config.
Sorry for the delayed response on this as I am stuck with other major issues.
Now we are able to acheive data rate upto 790Mbps per lane in 4 lane configuration but TRM says that it does support upto 800Mbps/lane.
I have used all the clock values mentioned in "Debug steps for customer MIPI sensor.docx" document and still getting some distortion in picture.
Can you please help me on this ?