What is ARM domain divider in i.MX6UL?

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What is ARM domain divider in i.MX6UL?

Senior Contributor I

Dear all,

What are 1/2 devider in front of ARM_CLK_ROOT described in the reference manual of MX6UL ?

ARM domain divider ?


Though described as "clock source goes to ARM Domain and returns to CCM", is possibly this devider for feedback to PLL1?

Because, it seems that this Devider does not exist from actual behavior.

Best Regards,


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NXP TechSupport
NXP TechSupport

Hello  George Fukutomi,

In previous IMX6 family such as 6SL,6SLX, the ARM_CLK_ROOT has s feedback clock path to CCM. This then can be MUXed to CLKO to be observed on a pad, and ARM_CLK_ROOT is after a static /2 divider, which is exactly the ARM domain divider in the pdf.

In 6UL, the ARM_CLK_ROOT is also after a static /2 divider, but the design does not export ARM_CLK_ROOT to CCM, hence we cannot route ARM_CK_ROOT on CLKO on 6UL (please refer to the definition of CCOSR in RM).

Therefore, the 6UL’s RM should be updated to change the comment in Figure 18-3. Clock Tree: “clock source goes to ARM Domain and returns to CCM” to “clock source goes to ARM Domain”

Please also refer to the thread below:

i.MX6UL: CCM_CLKO2 arm_clk_root on SD1_DATA2 pad


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