What does Threshold interrupt of IDMAC mean in IPU chapter?

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What does Threshold interrupt of IDMAC mean in IPU chapter?

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mach
Contributor I

Hi Guys,

My board is imx6q-sdb. I do not understand the concept of threshold interrupt from "37.4.2.14 IDMAC's internal events" in IMX6DQRM. In other words, I do not know how to raise this interrupt. Can anyone give me some details?

Best wishes,

Mc

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi

please refer to Table 37-14. Channel Parameters Memory parameter Threshold TH i.MX6DQ RM

it is used as synchronization signal, this could be end of frame or  threshold row,
that is row at which end-of-row may trigger an ARM/SDMA interrupt and/or
buffer flip (as an alternative to end-of-frame)

Best regards
igor
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mach
Contributor I

Thank you for reply.

I set TH field and THE field in CPMEM, and enable EOF/TH interrupt, and init 38(sync) irq interrupt. The result is that I can only catch the EOF interrupt. I do not know why TH interrupt does not raise.

PS:The reason why I want to use TH interrupt is that I want to use the OCRAM(256K) as my specific framebuffer to display a big picture(>1M) without using the DRAM (CH23: MEM--->DP, without EOBND interrupt). I plan to split the picture into several parts, then use TH_isr  to display the part one by one. The EBA0 of CH23 is set to the start address of OCRAM.

So there is  another problem: if I catch TH interrupt and place another part of picture into the OCRAM, can LCD display from the start address of OCRAM again? What about the double buffer?

Refer to : How to use the small iRAM to display a big picture by IPU on imx6q? 

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