WDOG1 timeout error

[ko-hey]

Hi all

I have a question about WDOG1 in i.MX6 Dual.

My customer want to make the Internal System Reset by timeout of WDOG1 but have a following issue with WDOG1.

・When they set a WDOGx_WCR register some value (ex. 0x01), the reset is generated with a delay than the settings.

・They have some boards and the delay time depends on the board.

I can't guess this cause.

Please give us an advise for this issue.

Ko-hey

[igorpadykov]

Hi Ko-hey

regarding WDOGx_WCR register settings one needs to pay attention to:

1. some bits can be written only once and can not be changed later until cold reboot.

    ROM can enable wdog if fuse WDOG_ENABLE is set. Uboot also can set wdog.

2. if this is linux, then during low power modes wdog can be stopped (depending on bit

    WDZST), so one can observe various delays.

Just for test one can try SDK wdog example:

"MX6_PLATFORM_SDK "

https://community.freescale.com/docs/DOC-94139

Best regards

igor

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[ko-hey]

Hi Igor

Sorry for late reply and thnak you for your support.

let me confirm several things.

1. What is the cold reboot ?

2. According to the RM, as you say, there are some registers that it can be written only once and it can change only after system reset or POR.

  What is difference between system reset and POR ?

3. What leads to the delay of the reset as there are some registers that is written only once and it can't change until reset ?

4. There is a following description in RM.

  From a following description, I guess that the prevention leads delay if the counter reaches zero and reload the timeout value before the i.MX boot completely

  Is there any possibility that my idea will occur ?

   ------------------------------

   The timer will time out when the counter reaches zero and the WDOG outputs a system reset signal,

   WDOG_RESET_B_DEB and asserts WDOG_B (WDT bit should be set in Watchdog Control Register (WDOG_WCR)).

   However, the timeout condition can be prevented by reloading the counter with the new timeout value (WT[7:0] of WDOG_WCR)

   if a service routine (see Servicing WDOG to reload the counter) is performed before the counter reaches zero.

   ------------------------------

Ko-hey

[igorpadykov · Accepted solution]

Hi Ko-hey

1. please look at Table 60-4. SRC reset functionality

i.MX6DQ Reference Manual (rev.3  7/2015)

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

2. please look at description of "system_rst_b" in Chapter 60

System Reset Controller (SRC)

3. delay may be caused that processor enters low power mode, in

low power mode WDog may be stopped

4. sorry I could not understand your idea

Best regards

igor

[ko-hey]

Hi Igor

1. Do you mean "COLD RESET" ?

2. I understand.

3. I understand.

4.

I apologize for any confusion.

The DOG operation flow that is my understanding is as below.

1. Unexpected error or programing error occur
2. The timeout counter start
3. The counter reach zero
4. Assert WDOG_RESET_B_DEB

 

The timeout will not occur if it reload the counter value during ② and ③.

Does the above understanding is correct ?

If yes, I guess that the WDOG timeout won't occur it the reload is repeated.

What do you think ?

Ko-hey

[igorpadykov]

Hi Ko-hey

1.yes

..

4. I think your understanding is right

Best regards

igor

[ko-hey]

Hi Igor

Thank you for your support.

ko-hey