Currently in our product we use the Vybrid VF610 with a single 128Mx8 DDR3 (IS43TR16640A). It is connected to the Vybrid with 16 address lines and 16 data lines split into a lower byte lane and an upper byte lane. Our product is moving to the i.MX6 SoloX and I would like to largely reuse the layout done with the Vybrid as far as DDR3 goes. Most reference designs, and the hardware guide, use 2 x 16bit wide DDR3 chips that together have a 32 bit wide databus. It seems the SoloX reference manual says using a 16 bit data bus is supported. Does NXP have any guidance, or reference designs that show the connections for a single chip using 16 data lines? Can I just do the following Vybrid->i.MX6 SoloX Mapping:
Vybrid - i.MX6 SX - DDR3 (IS43TR16640A)
DDR_D - DRAM_DATA00 - DQL0
DDR_D - DRAM_DATA07 - DQL7
DDR_D - DRAM_DATA08 - DQU0
DDR_D - DRAM_DATA15 - DQU7
DDR_A - DRAM_ADDR00 - A0
DDR_A - DRAM_ADDR15 - A15
I understand that imx6x DRAM_DQM0 would be connected to ddr3 DML and imx6x DRAM_DQM1 would be connected to ddr3 DMU. Same idea for DQS lines. I also understand the saberboard is swapping data lines within bytes and I would not do that. If the above mapping and DQM/DQS assumptions are correct, what should be done with the unused DRAM_DATA16 - 31 and associated SDQ, DQM lines?
Thank you for your help!
Do not recommend you to use the 16bit ddr3, recommend you to use the 32bit ddr3 so that the i.MX6SX can reach to the best performance. Here if you still want to use the 16bit ddr3, use the DRAM_DATA00-DRAM_DATA15 pins, let the DRAM_DATA16-DRAM_DATA31 pins floating.