Voltage supply to i.MX6SL when DDR3

[ko-hey]

Hi all

I'm using i.MX6SL and PF0100 and have question about voltage supply when I use DDR3.

Can MMPF0100F4AEP supply both NVCC_1P2V and NVCC_DRAM ?

According to the EVK's schematic, NVCC_1P2V and NVCC_DRAM are supplied from different LDO.

NVCC_1P2V is VGEN1 and NVCC_DRAM is SW3A/B.

However, MMPF0100F4AEP has only one 1.5V output.

So I plan to supply both NVCC_1P2V and NVCC_DRAM from SW3A/B.

Do I need to supply voltage separately ?

Ko-hey

[igorpadykov]

Hi Ko-hey

recommended to power it from separate clean LDO as it is used by

oscillator circuit as described in datasheet

Best regards

igor

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[ko-hey]

Hi Igor

Thank you for your reply.

So NXP recommend to add external LDO for supplying 1.5V to NVCC_1P2V.

Is it correct ?

Ko-hey

[igorpadykov]

Hi Ko-hey

yes correct.

Best regards

igor

[ko-hey]

Hi Igor

I understand that NXP recommend to supply voltage to NVCC_1P2V separately.

Let me confirm about supplying NVCC_1P2V again.

Does NVCC_1P2V have to supply voltage before POR_B is asserted ?

MMPF0100F4AEP has LDO that isn't programed such as VGEN2.

If I can supply voltage to NVCC_1P2V after POR_B is asserted, I want to use those LDOs.

I would rather not add a external LDO as much as possible.

So please advise me.

Ko-hey

[ko-hey]

Hi Igor

I found following Community.

https://community.freescale.com/message/405181#comment-405181

As far as I checked the community, it have to be supplied voltage to NVCC_1P2V separately.

Thank you for your corporation.

Ko-hey