Variscite var_som_mx6 ksz9031 PHY issue

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Variscite var_som_mx6 ksz9031 PHY issue

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ameerhamza
Contributor III

Dear all,

I am working on Ethernet development for Variscite var-som-mx6, without using any boot-loader or linux (using custom OS). Doing all the Ethernet driver development from the scratch. The default state of PHY for var-som-mx6 board is set to Power Down mode (LEDs are off at start-up even is Cable is plugged). The particular PHY shares RD0/MODE0, RD1/MODE1, RD2/MODE2, RD3/MODE3, RXCLK/PHYAD2 and RX_DV/CLK125_EN pins (e.g. RDx/MODEx Same pin can either be configure as RDx or MODEx).
Since PHY was currently in POWER DOWN mode, so we configure MODEx/RDx pins to GPIO level HIGH as mentioned in strapping option for RGMII mode. Then we enable clock for PHY by configuring RX_DV/CLK125_EN to GPIO High. Then we hard reset the PHY by GPIO1_25 pin after delaying for 10 millisecond. After resetting PHY gets alive and Lights are lid up. But when we reconfigure MODEx pins to RDx pins PHY becomes dead. After every reconfiguration of RDx pins PHY leds lost its brightness a little and after configuring all the pins to RDx pins, PHY gets totally dead. And we can not Read or Write from the PHY, but if we do not reconfigure pins from MODEx to RDx we can read or write the PHY device.
So my question is that why KSZ9031 PHY gets dead if we reconfigure from Strapping Configuration (MODE0/MODE1/MODE2 high, RGMIi mode) pins to RDx pins ?

I also have u-boot source available and I am using same sequence mentioned in setup_iomux_enet() {from line number 431-449, link uboot-imx/mx6var_som.c at imx_v2015.04_4.1.15_1.1.0_ga_var01 · varigit/uboot-imx · GitHub}, but some how not able to figure out what I am doing wrong.

Any help would be very highly appreciated.

Thanks,

Hamza.

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3 Replies

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Hamza

what do you mean by "reconfigure MODEx pins to RDx pins", as according to p.22 KSZ9031 datasheet:

After power-up or reset, the KSZ9031RNX is configured to RGMII mode if the
MODE[3:0] strap-in pins are set to one of the RGMII mode capability options.
See the “Strapping Options” section for available options.

Best regards
igor
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ameerhamza
Contributor III

Hi igor,

I am able to figure out where the problem is raising, In function power_init_board() uboot-imx/mx6var_som.c at imx_v2015.04_4.1.15_1.1.0_ga_var01 · varigit/uboot-imx · GitHubif I remove line number-1294 or line number-1298 (If LOW_POWER_MODE_ENABLE mode is disabled), and build the u-boot source for variscite board, u-boot also experiencing the same issue. But I am unable to figured out what power_init_board() function is doing also I could not found anywhere in TRM documentation about the PFUZEs. Where are PFUZEs defined and what can its relationship with the Ethernet Pins Latching ? Would be highly appreciated your guidance.

Thanks,
Hamza

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ameerhamza
Contributor III

Hi igor,

Thank you for looking into it. Yes you are right, its mention in datasheet. But for the Variscite var-som-mx6 board i currently have, MODE[3:0] sets to {0,0,0,0} after power up / reset (if u-boot is disabled). So I have to manually configure strapping pins to RGMII mode first before configuring same pins to ENET_RDx pins.

I wonder if this could be the case with Var-som-mx6 board as mentioned in below picture, but currently there are no schematics available for the processor board to confirm:pastedImage_1.png

But If we Hard reset the PHY (Also if u-boot is enabled) the MODE[3:0} sets to RGMII mode, but if u-boot is disabled the MODE[3:0} sets to reserved {0,0,0,0} after hard reset. I am confused why both the cases are different.

Any of your suggestion/help would be greatly appreciated.

Thanks,

Hamza.

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