VGA & LVDS screens together

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VGA & LVDS screens together

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FTO
Contributor I

Hi all,

We want to display data on two screens at the same time on Linux, one connected to a LVDS display, and one connected to a VGA screen, with our custom iMX53 board. But we do not succeed yet.

Displays have different timings, so we think we need to use the two DI separately.
VGA is necessarily linked to DI1, so we choose to use LVDS1 (where is linked our second display in hardware) in dual mode with DI0 source.

It seems to be the only way to display DI0 to LVDS1 and LVDS0 signals are not connected anyway.


We use VGA-XGA video mode for VGA display and a custom video mode for the LVDS display :

{
  /* 640x480 @ 60 Hz 25M pixel clk */
  "PRIMEVIEW-PD050VL1", 60, 640, 480, 40000,
  46, 18,
  33, 10,
  96, 2,
  0, // sync
  FB_VMODE_NONINTERLACED, // vmode
  FB_MODE_IS_DETAILED, // flag
}

Timing parameters are based on screen datasheet, but not 100% sure what sync, vmode and flag should be.

With this and the following kernel command line

console=ttymxc0,115200 consoleblank=0 video=mxcdi1fb:GBR24,VGA-XGA vga di0_primary video=mxcdi0fb:RGB666,PRIMEVIEW-PD050VL1,bpp=32 ldb=dual,di=0,ch0_map=SPWG,ch1_map=SPWG

and after unblanking VGA, we can observe that

  1. LVDS displays an stretched Tux (larger width only) on 1/3 of the screen width. Remaining 2/3 are junk.
  2. VGA displays a strange Tux, like if some little vertical bands have been cut and other parts glued back together. Really difficult to describe.

When drawing a checkerboard

  1. LVDS displays an stretched checkerboard (larger width only) on 1/3 of the screen width. I see 8 squares plus half one (actually rectangles) instead of 64 in x direction, and 48 as expected in y direction. Remaining 2/3 are junk.
  2. VGA displays a checkerboard with variable squares width (actually rectangles).

Moreover, if we use ldb=off instead of dual mode, VGA is just fine.

I wish to precise that the application writes correct data on fb0 and fb1, the question is NOT about it. Also we use NEITHER gstreamer NOR X-server at all. Data are drawn directly to framebuffers memory through IPU ioctls. The problem is the same with direct write to /dev/fb0 node.

The question is really about displaying the two framebuffers themselves on our two displays simultaneously.

Every documentation we read always return us to the same kernel command lines & co. So we have tried MANY combinations : di0_primary/di1_primary and turn on the other screen, add video mode also to ldb.c, try other video modes, try timings from PhytecBSP with the same LVDS, change LVDS cable, change LVDS screen, and so on...

Has anyone ever succeeded in this VGA/LVDS mix ?

Do you have an idea how to do it well ?

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max_tsai
NXP Employee
NXP Employee

These problems look related with "ipu_di1_clk" and FB format, according to your experientment.

For FB format, I am not sure if you did modify "fb_data" structure in your board description source. The definition order of fb_data implies how DI maps. You  may check your definition.

//"arch/arm/mach-mx5/mx53_ard.c"

static struct mxc_fb_platform_data fb_data[] = {

        {

         .interface_pix_fmt = IPU_PIX_FMT_RGB666,

         .mode_str = "XGA",

         .mode = video_modes,

         .num_modes = ARRAY_SIZE(video_modes),

         },

        {

         .interface_pix_fmt = IPU_PIX_FMT_GBR24,

         .mode_str = "1024x768M-16@60",

         .mode = video_modes,

         .num_modes = ARRAY_SIZE(video_modes),

         },

};

For "ipu_di1_clk", ldb driver appears to only support one by one mapping between ldb channel and di channel. LDB dual mode changes di0 and di1 clocks, and route ldb both channels to one di channel.

Suggest you add extra mode into ldb driver for your lvds1-to-di0 configuration, like "ldb=signale,di=0".


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FTO
Contributor I

Here some context :

The board

We designed a board based on an iMX53. Its basic operation is to transfer video from CSI to both VGA connector and LVDS display at the same time, along with some information.

The VGA connector is linked to the TVE signals of the IMX and LVDS display is linked to LVDS1 outputs of the IMX.

We observed similar results on QSB with LVDS0. Although we tried it, few tests have been made on this platform which is not the final product.

Kernel

The kernel used is based on imx-rel_imx_2.6.35_11.09.01

We have a custom board file, mainly a mix of SMD & LOCO board file.

We have a driver for a chip that is made for 2.6.35 kernel version, wich interracts with V4L2 input

This patch http://repository.timesys.com/buildsources/k/kernel/kernel-2.6.35/linux-2.6.35-mxc-ipu3-dual-display... is applied, because of this page https://linuxlink.timesys.com/docs/gsg/i.MX53START

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FTO
Contributor I

We have also noticed that LVDS display is fully correct when we apply the following sequence in userspace :

fbset -g 640 480 640 1400 32 -fb /dev/fb1

Here the LVDS displays an horizontally stretched checkerboard

fbset -g 640 480 640 1400 32 -fb /dev/fb0

Now the LVDS displays correctly

Both steps are necessary and of course VGA do not work anymore.


Based on this observation, I dived into the kernel code and saw that di0 and di1 share the same “parent clock” which seems to be modified by of drivers with different values.

Thus I tried to force it with one fix value in both drivers.

Furthermore, I had to divide LVDS pixclock by two compared to the screen specifications.


Now, when the system is started with di0_primary keyword, the LVDS is correct, but VGA screen complains about timings as during the “trick” presented above.

When the system is started with di1_primary keyword, the VGA is correct.

In both cases, when the second screen is turned on, the VGA complains about timings and LVDS is correct.


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FTO
Contributor I

Another observation is that

  • if parents' clocks are forced in ldb and tve drivers,
  • and if the last instruction of mxcfb_blank is not executed (that is mxc_fbi->cur_blank = blank;) mxcfb_blank returns 1 when LVDS is unblank with di1_primary kernel option

then both display are correct.

But :

  1. It sounds like a very bad situation-specific fix
  2. The application do not work anymore anyway [it works on LVDS when started with di0_primary, but VGA is broken]

EDIT : This morning I realize that it is not the last instruction, but return statement that leads to this behavior.

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1,042 Views
max_tsai
NXP Employee
NXP Employee

These problems look related with "ipu_di1_clk" and FB format, according to your experientment.

For FB format, I am not sure if you did modify "fb_data" structure in your board description source. The definition order of fb_data implies how DI maps. You  may check your definition.

//"arch/arm/mach-mx5/mx53_ard.c"

static struct mxc_fb_platform_data fb_data[] = {

        {

         .interface_pix_fmt = IPU_PIX_FMT_RGB666,

         .mode_str = "XGA",

         .mode = video_modes,

         .num_modes = ARRAY_SIZE(video_modes),

         },

        {

         .interface_pix_fmt = IPU_PIX_FMT_GBR24,

         .mode_str = "1024x768M-16@60",

         .mode = video_modes,

         .num_modes = ARRAY_SIZE(video_modes),

         },

};

For "ipu_di1_clk", ldb driver appears to only support one by one mapping between ldb channel and di channel. LDB dual mode changes di0 and di1 clocks, and route ldb both channels to one di channel.

Suggest you add extra mode into ldb driver for your lvds1-to-di0 configuration, like "ldb=signale,di=0".


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