VDDHIGH_CAP

[stevelandas]

I have about 12 prototype boards that have been working for about a month.

Three of the boards then failed and all failed in the same way. The symptom was that the board stopped booting.

I found that NVCC_LVDS2P5 was at about 1 volt and should be 2.5V. In this design NVCC_LVDS2P5 was powered from the PMIC VGEN3 output voltage (2.5). All other imx6 power rails requiring 2.5V were powered from VDDHIGH_CAP from the i.mx6 processor. I disconnected the LVDS rail from the PMIC and connected to VDDHIGH_CAP. The board then booted properly but was unstable would would not boot reliably. I measured the VDDHIGH_CAP voltage and it had dropped to about 2V. Any known reason for these voltages to drop like this?

[art]

The situation looks strange. Seems that your boards have been damaged by some ESD or something like. What is the state of VDDHIGH_IN on the damaged boards? Please check.

Best Regards,

Artur

[stevelandas]

Hi Artur,

Thank you for responding.

Yes, I think it is weir also. I ruled out ESD because it seemed unlikely that 3 boards would fail identically if it was ESD.

When I disconnect NVCC_LVDS2P5 from either the PMIC VGEN3_2V5 or from VDDHIGH_PH (testing using both of these sources) the voltages recover to 2.5V.

It acts like there is too large of a load.

This diagram shows the original design.

I cut the trace of VGEN3_2V5 at the PMIC so that I could add a jumper to power from VDDHIGH_CAP(GEN_2V5). As mentioned the problem initially improves and then degrades again.

On unmodified boards the 2P5 reads 2.5V.

I have one thought. The GEN_2V5 is used to power VDDIO on the LAN8720A and the NVCC_ENET imx6 rail is connected to 3.3V. The LAN8720A says these inputs 3.3V tolerant.

On first P1 boards the LAN8720A VDDIO was connected to 3.3V. But the signals coming from the imx6 measured much less that this and Ethernet did not work. When the LAN8720 VDDIO was changed to 2.5V the Ethernet worked fine. In looking at it in hindsight the signals coming from the imx6 should have been 3.3V. I just checked a working board and NVCC_ENET measures 3.3V but the signals from the imx6 to the LAN8720 measure 2.5V. Don’t know if the LAN8720A clamps these inputs due to VDDIO being at 2.5V or not.

Steve

[karina_valencia]

art​ can you help to continue with the follow up?

[stevelandas]

Hi Artur,

Sure, I added some content to the discussion a while back but go no further feedback. I was continuing the discussion thru email with Enrique.

I have a couple of concerns:

1. On the 1st rev of the board the LAN IO configuration was set to 3.3V.

The imx6 NVCC_ENET was also set to 3.3V.

But Ethernet did not work. I probed the signals from the imx6 and they were 2.5V. I change the GPIO configuration of the LAN to 2.5V and Ethernet has been working fine since that time.

But with NVCC_ENET at 3.3V I shouldn’t have had to use 2.5V.

I am using the following pins for the Ethernet interface: U20, W20, V21, W21,W22,U21,V20,V23,R2,W23,R4. All of these use NVCC_ENET or NVCC_GPIO (both configured to 3.3V)

Basically it is the exact interface as is in chapter 12, using the RMII interface from the hardware guide. In this document they don’t state if the IO is 3.3 or something else.

On the P2 boards I used the same setup as was in the P1, the LAN VDDIO used VDDHIGH_CAP. Ethernet works fine.

I then had 3 boards fail to boot. In troubleshooting I found that the 2.5V used to power NVCC_LVDS2P5 (required for DRAM) was not at 2.5V, measured between 1 and 2 volts depending on the board.

This 2.5V was sources from the PMIC, not VDDHIGH_CAP.

I reworked a board so that NVCC_LVDS2P5 came from VDDHIGH_CAP and the board boot properly one time. On the 2nd boot if failed and VDDHIGH_CAP no longer measured 2.5V.

So my question would be if the imx6 LAN digital signals to the LAN are at 3.3V levels and the LAN is expecting 2.5V could this pass through and damage both the PMIC 2.5V output and the VDDHIGH_CAP?

Also, for the Ethernet pins I am using can you confirm that 3.3V is correct?

2. I use a super-cap instead of a coin cell to power the LICELL input of the PMIC which in turn power VDD_SNVS_IN of the imx6. I noticed the super-cap charges slow enough that it is not the 1st power rail up as required.

I have reworked to correct this but is it possible this could have cause three boards to fail for the 2.5V as discussed above. On the next rev I am tying VDD_SNVS_IN to VDDHIGH_IN.

Thanks

Steve

[stevelandas]

Hi Artur,

Is it possible to discuss this today? I will be out on Fri and Monday for a funeral.

Thanks

Steve

[art]

Dear Steve Landas,

I'm sorry for the delay, I was on the vacation for past two weeks.

Regarding the issue, of course, anyway, both sides of the Enet interface (both the processor I/Os and the PHY I/Os) must be powered from exactly the same power supply. Otherwise, the interface may become permanently damaged. The NVCC_ENET power rail can operate on both 2.5V and 3.3V, it mostly depends on the PHY specs.

Finally, to make me able to better understand the issue, please provide me with the original schematic of your board in the "failed" power configuration.

Best Regards,

Artur

[stevelandas]

Hi Artur,

Can I email directly to you? I don’t want our schematics on the bull board.

Steve

[art]

OK, please upload it to my Google Drive:

FileShare - Google Drive

Artur