Using crystal oscillator on i.mx6ULL

[evgenyboger]

Hi,

summary: may I use schematics described in ERR009455 workaround on i.mx6ULL? Is it reliable?

Detailed version is below.

We are using the schematics from ERR009455 and i.mx6UL TO1.0 EVK in our custom i.mx6ULL-based design. In particular, Espon SG-210 external crystal oscillator (3.3V) output is supplied to XTALO via 1:3 voltage divider (500/1k). XTALI pad is connected to ground via external 18pF capacitor. 

The design was created a long time ago with TO1.0 i.mx6 UltraLite in mind. We then switched to i.mx6ULL without changing the schematics.

Unfortunately, i.mx6ULL documentation (datasheet, reference manual and hardware development guide) provide insufficient, and even conflicting information concerning use of crystal oscillator. For instance,

1) IMX6ULLIEC 1.2 page 18: "XTALO must be directly driven by the external oscillator and XTALI is disconnected.". No mention of capacitor on XTALI pin.

2) IMX6ULLHDG rev 0 page 14: "A single ended external clock source can be used to drive XTALI. In this configuration, XTALO should be left externally floating".

So, I would like to request more information about using external 24M clock source on i.mx6ULL, as follows:

1) May I continue use our schematics (described in ERR009455 workaround) on i.mx6ULL? Is it reliable?

2) Do we still need to connect external capacitor to XTALI when externally driving XTALO?

3) What divider should we use in case of supplying external clock to XTALO? As far as I understand, in this configuration the internal inverting amplifier output is overridden by the external signal, which effectively lower voltage on XTALO pin. If so, should we meet 0.8*NVCC_PLL level requirements on XTALO signal?

4) IMX6ULLRM rev. 1 section "60.4.2 Bypass Configuration (32 kHz)" describes three option to supply external clock to RTC_XTALI/RTC_XTALO. Is the same applicable to 24MHz XTALI/XTALO as well?

[Yuri]

Hello,

  Please look at my comments below.

1.,2., 3.

    It is possible to use clock source circuit from i.MX 6UL TO1.0 EVK, assuming

that the 18pF capacitor to the XTALI is not mounted and clock output divider

provides signal, which satisfies “XTALI and RTC_XTALI (Clock Inputs) DC Parameters”

section of the i.MX 6ULL Datasheet(s). That is - to apply the configuration, as stated

in the IMX6ULLIEC: "XTALO must be directly driven by the external oscillator and XTALI

is disconnected".

4.

  Generally - yes - the options, described in the section "60.4.2 Bypass Configuration

(32 kHz)" may be used.

Have a great day,
Yuri

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[evgenyboger]

Thank you!

1-2-3) We tested the circuit without 18pf capacitor on XTALI, i.e. 3.3V crystal oscillator with 500/1k divider.

We observe that the actual signal on XTALO pin is much lower than 1.1V (3.3V/3) in amplitude, probably because it 'overdrives' the output of internal inverting amplifier inside the i.mx6ULL. Moreover, the signal amplitude varies greatly between boards, possibly because of the variation of the internal amplifier parameters.

Should we decrease the divider so the actual amplitude of the XTALO signal is larger than 0.8*NVCC_PLL ?

4) This section says to indeed connect the external 18pF capacitor to the XTALI when the external clock is supplied to XTALO pin which contradicts your answer and the datasheet. Should we assume this part is invalid?

[Yuri]

Hello,

   According to i.MX 6ULL Datasheets: 

XTALI high-level DC input voltage Vih should be in range min = 0.8 x NVCC_PLL,  max = NVCC_PLL. 

  I do not think, that external cap on XTALI provides problems, moreover the combination of the internal

biasing resistor and the external capacitor will filter the signal applied to the XTALO.    

  The solution with XTALO overdriving  is acceptable, but  the best case is XTALI driving, assuming XTALO

is left floating.

Regards,

Yuri.

[evgenyboger]

 The solution with XTALO overdriving  is acceptable, but  the best case is XTALI driving, assuming XTALO

is left floating.

Sure, we'll definitely switch to this schematics (or even using quartz crystal) in the next board revision. However we are now stuck with several hundreds already assembled boards which doesn't work reliably and we are pretty sure the problem is related to external oscillator (as various random adjustments seem to help). 

So I would really appreciate if you help us to establish safe component values for the schematics we have (i.e. the one from UL TO1.0 EVK).

 According to i.MX 6ULL Datasheets: 

XTALI high-level DC input voltage Vih should be in range min = 0.8 x NVCC_PLL,  max = NVCC_PLL. 

Unfortunately it doesn't answer my question. First of all, when using TO1.0 UL EVK schematics, we are driving XTALO, not XTALI. 

Second, the measured voltage levels on XTALO are altered by internal i.mx schematics (as if it has effective input impedance of 500 Ohms or so). Should we take it into account and make sure the measured voltage level on XTALO meets the specs you've just cited?

[Yuri]

Hello,

  I found the following recommendation:

change the divider resistors R514 to 300 OHm and R520 to 150 OHm

(based on MX6UL EVK schematic).

Regards,

Yuri.

[evgenyboger]

Thank you, Yuri. 

Yes, we found this too. However, we are not ready to deploy this change based solely on the schematics from EVK because:

1) The actual EVK we've got uses 1000/500 Ohm resistors, in contrary to the schematics

2) The workaround mentioned in ERR009455 states 1000/500 Ohms as well.

So we afraid that this 300/150 Ohm values might be a mistake, or it might be not optimal for i.MX6ULL or the crystal oscillator we are using.

Yuri, at this point I'm pretty sure we checked every piece of public data NXP ever provided on this matter. I think we need to summon someone with deeper understanding of this very obscure topic. It it possible to ask people who are behind hardware engineering, or the ones who developed EVK or the relevant errata?

[Yuri]

Hello,

  I've sent You some comments directly.

Regards,

Yuri.