Using PCIe on i.MX8MP with internal clock on Linux-imx 6.1.36

[Redman]

Hello everyone,

I'm trying to set up the dts to use the PCIe interface on a uSOM equipped with an i.MX8MP processor. I know for sure that the hardware is ok because I'm using the uSOM with a development board and everything is ok when using the linux-imx 5.15.32.
The problems arise when using the latest linux-imx 6.1.36: I get a " phy phy-32f00000.pcie-phy.2: phy poweron failed --> -110" in the dmesg, a symptom that the PCIe PHY is not being properly clocked.

The dts fragment for the PCIe is the following:

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_UNUSED>;
	clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
	clock-names = "ref";
	status = "okay";
};

&pcie {
	reset-gpio = <&pca9555 0 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
		 <&clk IMX8MP_CLK_PCIE_ROOT>,
		 <&clk IMX8MP_CLK_HSIO_AXI>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
	assigned-clock-rates = <10000000>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
	status = "okay";
};

&pcie_ep {
	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
		 <&clk IMX8MP_CLK_PCIE_ROOT>,
		 <&clk IMX8MP_CLK_HSIO_AXI>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
			  <&clk IMX8MP_CLK_PCIE_AUX>;
	assigned-clock-rates = <500000000>, <10000000>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
				 <&clk IMX8MP_SYS_PLL2_50M>;
	status = "disabled";
};

 
Can someone point me out what is missing, please?

Thank you!

[shlomz]

HI,

I have the same issue when using the pcie as pcie_ep.

can you please add the relevant changes for this mode ?

thanks

[Redman]

Hello!
Problem solved, thanks for your help!

[JorgeCas · Accepted solution]

Hello, I hope you are doing well. 

This issue was reported before, I will attach a working reference DTS and 4 patches that need to be applied.

pcie0_refclk: pcie0-refclk {
    compatible = "fixed-clock";
    #clock-cells = <0>;
    clock-frequency = <100000000>;
};

reg_pcie0: regulator-pcie {
    compatible = "regulator-fixed";
    regulator-name = "MPCIE_3V3";
    regulator-min-microvolt = <3300000>;
    regulator-max-microvolt = <3300000>;
    gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
    enable-active-high;
    regulator-always-on;
};

&pcie_phy {
    fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
    clocks = <&hsio_blk_ctrl>;
    clock-names = "ref";
    status = "okay";
};

&pcie {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_pcie0>;
    reset-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
    clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
    <&clk IMX8MP_CLK_PCIE_ROOT>,
    <&clk IMX8MP_CLK_HSIO_AXI>;
    clock-names = "pcie", "pcie_aux", "pcie_bus";
    assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
    assigned-clock-rates = <10000000>;
    assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
    vpcie-supply = <&reg_pcie0>;
    status = "okay";
};

Patches:

https://www.spinics.net/lists/devicetree/msg558950.html 
https://www.spinics.net/lists/devicetree/msg558947.html 
https://www.spinics.net/lists/devicetree/msg558949.html 
https://www.spinics.net/lists/devicetree/msg558948.html 

Please let me know if helps with your issue.

Best regards.