Hey people! I am in trouble trying to connect a custom LVDS display made by SAMSUNG to imx53qsb on the J9 (LVDS) connector (LCD Model: LT101NT02):
Here is my steps:
- Configuring a WSVGA resolution on mx53_loco.c as (watch the last entry of the array):
static struct fb_videomode video_modes[] = {
{
/* NTSC TV output */
"TV-NTSC", 60, 720, 480, 74074,
122, 15,
18, 26,
1, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_INTERLACED,
0,},
{
/* PAL TV output */
"TV-PAL", 50, 720, 576, 74074,
132, 11,
22, 26,
1, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
0,},
{
/* 1080i50 TV output */
"1080I50", 50, 1920, 1080, 13468,
192, 527,
20, 24,
1, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
0,},
{
/* 1080i60 TV output */
"1080I60", 60, 1920, 1080, 13468,
192, 87,
20, 24,
1, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
0,},
{
/* 800x480 @ 57 Hz , pixel clk @ 27MHz */
"CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
FB_SYNC_CLK_LAT_FALL,
FB_VMODE_NONINTERLACED,
0,},
{
/* 800x480 @ 60 Hz , pixel clk @ 32MHz */
"SEIKO-WVGA", 60, 800, 480, 29850, 89, 164, 23, 10, 10, 10,
FB_SYNC_CLK_LAT_FALL,
FB_VMODE_NONINTERLACED,
0,},
{
"XGA", 60, 1024, 768, 15385,
220, 40,
21, 7,
60, 10,
0,
FB_VMODE_NONINTERLACED,
0,},
{
/* 720p30 TV output */
"720P30", 30, 1280, 720, 13468,
260, 1759,
25, 4,
1, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED,
0,},
{
"720P60", 60, 1280, 720, 13468,
260, 109,
25, 4,
1, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED,
0,},
{
/* VGA 1280x1024 108M pixel clk output */
"SXGA", 60, 1280, 1024, 9259,
48, 248,
1, 38,
112, 3,
0,
FB_VMODE_NONINTERLACED,
0,},
{
/* 1600x1200 @ 60 Hz 162M pixel clk*/
"UXGA", 60, 1600, 1200, 6172,
304, 64,
1, 46,
192, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED,
0,},
{
/* 1080p24 TV output */
"1080P24", 24, 1920, 1080, 13468,
192, 637,
38, 6,
1, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED,
0,},
{
/* 1080p25 TV output */
"1080P25", 25, 1920, 1080, 13468,
192, 527,
38, 6,
1, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED,
0,},
{
/* 1080p30 TV output */
"1080P30", 30, 1920, 1080, 13468,
192, 87,
38, 6,
1, 1,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED,
0,},
{
"1080P60", 60, 1920, 1080, 7692,
100, 40,
30, 3,
10, 2,
0,
FB_VMODE_NONINTERLACED,
0,},
{
/* 1024x600 WSVGA @ 60 Hz, running @ 54.2Mhz pixclock
* Vertical Total: BackPorch + VSYNC + DATA + FrontPorch =
* 6 + 30 + 600 + 37 ----> 673
* Horizontal Total: BackPorch + HSYNC + DATA + FrontPorch =
* 125 + 126 + 1024 + 125 ----> 1400 */
.name = "WSVGA",
.refresh = 60,
.xres = 1024,
.yres = 600,
.pixclock = 18450,
.left_margin = 125,
.right_margin = 125,
.upper_margin = 6,
.lower_margin = 37,
.hsync_len = 126,
.vsync_len = 30,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
};
- Change the fb_data array as:
static struct mxc_fb_platform_data fb_data[] = {
#if 0
{
.interface_pix_fmt = IPU_PIX_FMT_RGB565,
.mode_str = "CLAA-WVGA",
.mode = video_modes,
.num_modes = ARRAY_SIZE(video_modes),
},
{
.interface_pix_fmt = IPU_PIX_FMT_BGR24,
.mode_str = "XGA",
.mode = video_modes,
.num_modes = ARRAY_SIZE(video_modes),
},
#endif
{
.interface_pix_fmt = IPU_PIX_FMT_RGB666,
.mode_str = "WSVGA",
.mode = video_modes,
.num_modes = ARRAY_SIZE(video_modes),
},
{
.interface_pix_fmt = IPU_PIX_FMT_LVDS666,
.mode_str = "WSVGA",
.mode = video_modes,
.num_modes = ARRAY_SIZE(video_modes),
},
};
So both resolutions are IDENTICAL (I suppose), (note the RGB666 and LVDS666 on the interface_pix_format field...). then recompile the kernel with:
./ltib -p kernel -m scbuild
then changed the cmdline options in the bootloader as:
console=ttymxc0,115200 video=mxcdi0fb:LVDS666,WSVGA di0_primary video=mxcdi1fb:RGB666,WSVGA video=mxcdi2fb:RGB666,WSVGA root=/dev/nfs ip=192.168.143.173 nfsroot=192.168.143.6:/tftpboot/nfs-IMX53
,v3,tcp noinitrd
So the connector J9 (LVDS0 == DI0?) should have valid timings for a such display
Plug the cable on the J9 connector using 3 channels LVDS plus PWM for contrast and LCD_BLT_EN Lines connected tothe LVDS Panel pins named: PWM and LCD_BL.
Powering the backlight VLED unit with the correct Voltage using a Voltage Generator with 2A of MAX CURRENT.
But I do not see anything on the screen. Nothing.
Now here is the logs of fbset:
root@freescale ~$ fbset -fb /dev/fb0
mode "1024x600-58"
# D: 54.201 MHz, H: 38.715 kHz, V: 57.526 Hz
geometry 1024 600 1024 1800 16
timings 18450 125 125 6 37 126 30
accel false
rgba 5/11,6/5,5/0,0/0
endmode
root@freescale ~$ fbset -fb /dev/fb1
mode "1024x600-58"
# D: 54.201 MHz, H: 38.715 kHz, V: 57.526 Hz
geometry 1024 600 1024 1800 16
timings 18450 125 125 6 37 126 30
accel false
rgba 5/11,6/5,5/0,0/0
endmode
root@freescale ~$ fbset -fb /dev/fb2
mode "240x320-60"
# D: 4.608 MHz, H: 19.200 kHz, V: 60.000 Hz
geometry 240 320 240 960 16
timings 217013 0 0 0 0 0 0
accel false
rgba 5/11,6/5,5/0,0/0
endmode
What I am doing wrong?
Best regards,