Using LPUART2 with Arm Cortex A35 in i.MX 8ULP

[daisukemizobuch]

Hello,

I want to use LPUART2 with Arm Cortex A35. The other LPUARTs are already in use, so you need to use LPUART2.

LPUART2 interrupts are not assigned to A35. But LPUART2 interrupt is not assigned to A35.

I am referring to the following manual:
i.MX 8ULP Processor Reference Manual Rev. 1, 09/2023
Table 3. GIC interrupt vector assignments

Is there a recommended implementation that uses LPUART2 from A35?

Regards,
mizo

[Zhiming_Liu]

Hi @daisukemizobuch 

There is no such implementation in BSP.

Best Regards
Zhiming

[daisukemizobuch]

Hi @Zhiming_Liu

Thank you for your quick reply.

> There is no such implementation in BSP.

Since it's not implemented in the BSP, I'm trying to implement it
myself. However, implementation is difficult if interrupts cannot be
used.

Can I receive LPUART2 interrupts from the A35?

Best Regards,
mizo

[Zhiming_Liu]

Hi

The best way is to drive lpuart2 in DSP domain and use rpmsg framework to transfer data.

You can use SDK/rpmsg_lite_str_echo_rtos_imxcm33 and linux/drivers/rpmsg/imx_rpmsg_tty.c as an example.

Best Regards
Zhiming

[daisukemizobuch]

Hi @Zhiming_Liu

Thank you for reply.

I have made rpmsg_lite_pingpong_rtos and rpmsg_lite_str_echo_rtos work. I'm sorry I didn't tell you.

I understand that it is okay to use the rpmsg framework. But I feel that there is no point in using the M33 just for pass-through purposes.

If A35 can receive interrupts, I would like to use it directly.

Can I receive LPUART2 interrupts from the A35?

Best Regards,
mizo

[daisukemizobuch]

Hi @Zhiming_Liu

I looked at other threads, but it seems that you can't use the core connected to the M33 or DSP from the A35.

https://community.nxp.com/t5/i-MX-Processors/How-to-switch-control-of-LPSPI3-from-the-M-core-to-the-...
https://community.nxp.com/t5/i-MX-Processors/i-MX8ULP-access-pbridge2-from-m33/m-p/1923507
https://community-nxp-com.translate.goog/t5/i-MX-Processors/LPSPI2-on-i-MX-8ULP-A35-vs-M33/m-p/15387...

I understand that it is not possible to use A35 with the NXP BSP. Are there any hardware limitations for the i.mx8ulp?

Best Regards,
mizo

[Zhiming_Liu · Accepted solution]

Hi @daisukemizobuch 

Here is the block diagram of i.MX 8ULP, there are 4 uart in A35 core and 2 uart in M33. 

More accurately, the LPUART2 is under PBRIDGE2 in DSPD. In other word, the LPUART2 is designed for DSP core, not A35 core. Of course,  we could access LPUART2 registers from A35 with modifying T-MBC3 setting. 

But A35 can't control the basic resources about LPUART2 like clocks and interrupt. The LPUART2 clock relies on DSP busclk(PCC2 clock unit) and the dsp busclk is generated by RTD_CGC(Real Time Domain Clock Generate Controller). The default interrupt is designed in DSP core.

There is no X-PAC( XRDC Peripheral Access Controller) in DSP domain which means we can't map the entire pbridge2 bus to A core kernel. 

Best Regards
Zhiming

[daisukemizobuch]

Hi @Zhiming_Liu

Thank you for your quick reply.

I understand that not all functions are available from the A35 core. I implement it using the rpmsg framework.

Thank you for providing very important information.

Best Regards
mizo