Hi, NXP TechSupport
I have implemented single beat write / read of i8080 bus cycle on imx93-EVK. The bus timing looks okay with total cycle time 800ns. There is a FASTACC bit in CTRL register, which suppose faster register access. But bus cycle becomes much longer instead of shorter with FASTACC bit enbaled. I suppose I haven't got right way to setup FASTACC bit. Please let me know to use the function of FASTACC bit in CTRL register. Thanks!
Regards
Cheng Shi
for FlexIO to drive 8080 bus, you can refer to the link as below
Using FlexIO to Drive 8080 Bus LCD on K32L2A
for the FASTACC bit, refer to the RM, You must enable the FLEXIO functional clock before accessing any of the FLEXIO registers. Provided the FLEXIO functional clock is at least equal to the bus clock, maybe you need check the functional clock
As my understanding of RM, the flexio1's functional clock should be flexio1.flexio_clk (RM p.1744), is it right?
For FlexIO DTS :
refer to the RM, Provided the FLEXIO functional clock is at least equal to the bus clock, the CTRL[FASTACC] field can be set to support fast register accesses., so you also need to check the bus clock
what is the bus clock in RM? Is it AXI clock or something similar?
bus clock means pclk, this should be the ipg clock, refer to the dts file, it seems the clock is set the same, you also can dump the clocks to check, I didn't find other request for FASTACC enable