As my understanding of RM, the flexio1's functional clock should be flexio1.flexio_clk (RM p.1744), is it right?
For FlexIO DTS :
flexio1: flexio@425c0000 {
compatible = "nxp,imx-flexio";
reg = <0x425c0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_FLEXIO1_GATE>,
<&clk IMX93_CLK_FLEXIO1_GATE>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX93_CLK_FLEXIO1_GATE>;
assigned-clock-parents = <&clk IMX93_CLK_FLEXIO1>;
....
};
the flexio functional clock is refered to "IMX93_CLK_FLEXIO1_GATE".
Both ipg_clk and per_clk are enabled in driver's probe function, but FASTACC behaviors weird.
Regards