Using 2nd LAN port in board design

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Using 2nd LAN port in board design

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jautry
Contributor III

Am attempting to use 2nd mac on processor to provide 2 lan ports on a new design.  I cannot find any information in the reference guide to where the RMII signals for the 2nd MAC interface are connected.  eg. where is ENET2_RX_DATAx connected to GPIO pin?  Perhaps someone can point me to this information.

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi,
Thanks for your reply.
1) These are not shared?
-- No.
2) Where is ENET2_RX_DATAx connected to GPIO pin?
-- Please refer to Table 10-1. Muxing Options in the RM.
3) Is this supposed to be tied to G13 on the proc since that is defined to be the CRS pin?
-- No.
Have a great day,
TIC

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi,
Thanks for your reply.
1) These are not shared?
-- No.
2) Where is ENET2_RX_DATAx connected to GPIO pin?
-- Please refer to Table 10-1. Muxing Options in the RM.
3) Is this supposed to be tied to G13 on the proc since that is defined to be the CRS pin?
-- No.
Have a great day,
TIC

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Note:
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- We are following threads for 7 weeks after the last post, later replies are ignored
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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Before answering your question, can you tell me which RT MCU do you use?
Have a great day,
TIC

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- We are following threads for 7 weeks after the last post, later replies are ignored
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jautry
Contributor III

One other question on this interface, RMII defines that MDIO, MDC, and REF_CLK can be shared.  I note that ENET2_MDC, ENET2_MDIO, and ENET2_TXCLK are defined along with ENET versions.  These are not shared?

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jautry
Contributor III

I also noted that on the MIMXRT1060 EVK schematic, it has the phy CRS pin tied to pin C13 on the proc.  Is this supposed to be tied to G13 on the proc since that is defined to be the CRS pin?

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jautry
Contributor III

MIMXRT1062DVL6B

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