Use of ADV# pin in parallel NOR flash (ADMUX) interfacing

[VishalAvg]

Hello,

I want to interface parallel NOR flash (256KB*16) with IMXRT1062 but this processor have same port pins for address and data bus. So, I find that ADV#. What is use of this ADV# pin? 

I have found this notes for SRAM. Is it same applicable for NOR flash also?

ADV# pin enables Address Path (ADQ=Address Buffer) by asserting ADV# input Low. When ADV# is High, Data Path is enabled (ADQ=I/O Buffer).

[VishalAvg]

Please reply me!

[Omar_Anguiano]

Yes, the use of ADV on nor flash is similar to the SRAM.

Best regards,
Omar

[VishalAvg]

Ok, Thanks for help.

Please tell me one more thing.

How can I interface parallel NOR flash for separate address bus and data bus? Can we interface directly?

If I interface same terminal of imxrt1062 with NOR flash address and data pins then command will be transfered on both bus of parallel NOR flash.

I have attached one image. 

I am thinking to add two 74LVC164245 IC in between imxrt1062 and flash chip. So that we can separate address/data transfer to flash chip.

[Omar_Anguiano · Accepted solution]

From the SEMC side, the data and address pins will be on MUX mode so it is not possible to have dedicated address/data pins for NOR flash. The communication will look like this:

Regarding using an external component to separate these signals. It looks viable however I cannot confirm if it is your adequate solution since it was not tested on our side.

Best regards,
Omar

[VishalAvg]

Ok thanks