Unused SNVS_TAMPER pins in i.Mx7D

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Unused SNVS_TAMPER pins in i.Mx7D

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sharmilad
Contributor I

Hi,

 We are working with NXP’s i.MX7 Dual CPU for one of our product. We have few SNVS_TAMPER pins which is left unused , so we are planning to use these pins in sleep/wakeup module. So I have few queries regarding the same.

1. Can we configure SNVS_TAMPER pins as GPIO? IF so where will I get the information about the procedure to do so.

2. Does these pins have edge triggered INT capability?

Please help me in this.

Thanks & Regards,

Sharmila D

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8 Replies

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joanxie
NXP TechSupport
NXP TechSupport

you can refer to the 8.1.1.1 Muxing Options of reference, imx7d isn't like imx6, SNVS_TAMPER pins couldn't used as GPIO

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782 Views
sharmilad
Contributor I

Hi Joanxie,

    Thank you for your reply. I agree that SNVS_TAMPER pins cannot be configured as GPIO.

   We are planning to use one of tamper pins as wakeup source. Can we configure SNVS_TAMPER pins as Interrupt/wakeup source?

   Can we ensure tamper default functionality (LP security violation) is disabled by configuring SNVS LPTDCR register?

Thanks & Regards,

Sharmila D

 

 

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741 Views
joanxie
NXP TechSupport
NXP TechSupport

do you need use interrupt wake up the system from LPSR, right? try to use GPIO do this job, for SNVS:

0x30370048 :Bit[7] by default should be 1, which disables this function, for enabling GPIO wakeup from LPSR mode, bit[7] must write 1, then read out value is 0, means the function is enabled.

 

 

725 Views
sharmilad
Contributor I

 Hi @joanxie ,

Thank you for your valuable reply.

We would like to keep Tamper functionality for few tamper pins and enable GPIO wakeup functionality for other tamper pins. Whether SNVS: 0x30370048 :Bit[7] will enable GPIO wakeup for all tamper pins? Any additional configuration required to configure specific pin (Eg: SNVS_TAMPER2) as GPIO wakeup?

Thanks & Regards,

Sharmila D

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694 Views
joanxie
NXP TechSupport
NXP TechSupport

got reply:

"

There was one case to use GPIO (GPIO1_IO04) waking up system from LPSR. Your customer can take it as reference to make GPIO1_IO07 work, suppose only IOMUX and GPIO settings need to be changed accordingly:

IOMUXC_LPSR:
0x302c0010 ? – for IOMUX setting, need to set to 0x0;

GPIO1:
0x30200004 ? for GPIO input/output setting, bit[4] must be 0 to select GPIO as input;
0x3020000c ? for level setting to trigger interrupt, bit[9:8] must be 0 to select low level sensitive;
0x30200014 ? for enabling interrupt, bit[4] must be 1 to enable the GPIO1_4 interrupt;

SNVS:
0x30370048? Bit[7] by default should be 1, which disables this function, for enabling GPIO wakeup from LPSR mode, bit[7] must write 1, then read out value is 0, means the function is enabled.

"

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679 Views
sharmilad
Contributor I

Hi @joanxie 

Our requirement is to transition from low power mode to run mode by using tamper event.
As per i.Mx7 datasheet  (page no 29 -  https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf )

tamper event/IRQ can be used to transit from low power to run mode.
In our case we have connected GPRS cell ring indication pin to one of the tamper pin(SNVS_TAMPER2).
We do not want any LP security violation to be generated and we want to use tamper pins as only wakeup source.
We would like to understand the software side configuration to meet the above requirement.

Thanks & Regards,

Sharmila D

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joanxie
NXP TechSupport
NXP TechSupport

I confirmed that enabling tamper generate LP security violation, so try to use general GPIO to wake up

 

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757 Views
sharmilad
Contributor I

 

Hi @joanxie 

Gentle Reminder for the above query.

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