Unused PCIE pins SoloX

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Unused PCIE pins SoloX

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scottgauche
Contributor I

Hi,

Section 3.2 Table 5 of the SoloX datasheet says to tie PCIE_VPTX and PCIE_VP to ground for the 19x19 part.  It seems like this would just short LDO_PCIE inside the SoloX and cause overcurrent conditions.  Is it correct to short these pins to ground if PCIE is unused?

Thanks,

Scott

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Yuri
NXP Employee
NXP Employee

Hello,

"The recommendations will be as follows:

1) PCIE_VP and PCIE_VPTX (if present on the package) should be connected with a 4.7 uF capacitor to ground.

This capacitor is required to stabilize the output of LDO_PCIE.

2) PCE_VPH should be floated. Designs that already have PCIE_VPH connected to ground are not expected to cause

any damage to the SoC.

3) Disabled LDO_PCIE after the application is running. The internal LDO_PCIE is enabled after reset. The application

should disable the LDO by setting the register field PMU_REG_CORE[REG1_TARG] = “0000” (power gated off). The LDO_PCIE

should be disabled as soon as possible in the application to minimize power consumption.

We should have the final document up shortly."

Regards,

Yuri.

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inmaku
Contributor III

Hi Yuri, Hi All,

I appologize when I warm-up this issue one more time, but there is a bit more to it:

I think teh supply questions ar epretty good covered, nbut how about the PCIE_REXT pin? For PCIe working, a 200R resistor is needed. When not using PCIe - same applies to SATA - can I just leave those Pins open (not populated resistors)?

Thanks in advance,

Ingo 

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Yuri
NXP Employee
NXP Employee

Hello,

   Please use the recent i.MX6SX Datasheet(s) and the Hardware Development Guide
regarding unused pins. In particular, PCIE_REXT may be left floating.  

http://www.nxp.com/assets/documents/data/en/user-guides/IMX6SXHDG.pdf 

i.MX 6SoloX Family of Applications Processors|NXP  

Regards,

Yuri.

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Yuri
NXP Employee
NXP Employee

Hello,

   This is common approach for devices of i.MX6 series for unused PCIe module :

PCIE_REXT, PCIE_RXM, PCIE_RXP, PCIE_TXM, PCIE_TXP should be left float

and PCIE_VP, PCIE_VPH, PCIE_VPTX may be grounded if there is no need

for boundary scan testing. This may be found in Table 2-17 (Recommended connections

for unused analog interfaces) of “Hardware Development Guide for i.MX 6SoloX Applications Processors”

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6SXHDG.pdf

  But  below is comment from the team :  "The statement to ground the PCIe supplies is incorrect.
This was added with the original package where none of the PCIE supplies were connected inside the package.
When the new packages were added, that statement should have been removed.
These supplies should not be grounded."


Have a great day,
Yuri

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scottgauche
Contributor I

Yuri,

What should we do with the pins PCIE_VP and PCIE_VPTX when PCIe is unused?

What should we do with the pins PCIE_VPH when PCIe is unused?

Thanks,

Scott

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Yuri
NXP Employee
NXP Employee

Hello, Scott !

The situation depends on device version (package type).

IMX6SX of 17x17mm NP does not support PCIe

From footnote of Table 5 (Recommended Connections for Unused
Analog Interfaces) of the Datasheet (IMX6SXCEC, Rev. 1, 9/2015) :

"On the 19x19, 17x17 WP and 14x14 packages, these signals [PCIE_VP,
PCIE_VPH, PCIE_VPTX] must be powered if boundary scan is used. On
the 17x17 NP package, PCIE_VP and PCIE_VPTX are connected inside
the package to PCIE_VP_CAP and PCIE_VPH is connected inside

the package to VDD_HIGH_CAP."

According to Table 113 (i.MX 6SoloX signal availability by package) of the
Datasheet, only PCIE_VP_CAP is present on 17x17mm NP; it must be connected

to an external 4.7uF filter capacitor.

Nevertheless, to be fully on safe side, it may be recommended to apply voltages for PCIe

(if supported, but not used) as stated in Table 11 (Operating ranges) of the Datasheet.

http://cache.nxp.com/files/32bit/doc/data_sheet/IMX6SXCEC.pdf


Regards,

Yuri.

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karina_valencia
NXP Apps Support
NXP Apps Support

Yuri​ can you continue helping customer  to  follow  previous update?

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scottgauche
Contributor I

I guess I should add a little more detail.

We currently have a board with the 3 PCIE pins grounded on the 19x19 package because that is what the hardware guide said to do.  The board is not functioning.


We are getting the board re-worked.  Our plan is to cut the trace to the via under the BGA for pins PCIE_VP and PCIE_VPH to float those pins.  We don't have a choice but to leave these floating, as we are not able to add decoupling capacitors to them.

We are wondering what to do with PCIE_VPTX, it is currently grounded with a via under the BGA.  We can either float that pin by cutting the trace to the via during re-work or leave it grounded.  What would be the better/correct option?

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Yuri
NXP Employee
NXP Employee

Hello,

   Please refer to the following

i.MX 6SoloX: Important Notice Regarding Unused PCIe Supply Connections

Regards,

Yuri.

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scottgauche
Contributor I

Sorry, my last post was incorrect, the announcement says what to do with PCIE_VPH and PCIE_VP but does not say what to do with PCIE_VPTX.  I corrected my last post.

The announcement only covers 2 of the 3 PCIE pins on the 19x19 SoloX.  Please re-verify the recommendation for each of the pins again. 

We aren't convinced that PCIE_VPH can't remain connected to ground.  We think PCIE_VP and PCIE_VPTX should float and PCIE_VPH should be ground (like PCIE_VPH was in the Dual and Quad).

Thanks.

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Yuri
NXP Employee
NXP Employee

Hello,

"The recommendations will be as follows:

1) PCIE_VP and PCIE_VPTX (if present on the package) should be connected with a 4.7 uF capacitor to ground.

This capacitor is required to stabilize the output of LDO_PCIE.

2) PCE_VPH should be floated. Designs that already have PCIE_VPH connected to ground are not expected to cause

any damage to the SoC.

3) Disabled LDO_PCIE after the application is running. The internal LDO_PCIE is enabled after reset. The application

should disable the LDO by setting the register field PMU_REG_CORE[REG1_TARG] = “0000” (power gated off). The LDO_PCIE

should be disabled as soon as possible in the application to minimize power consumption.

We should have the final document up shortly."

Regards,

Yuri.

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Yuri
NXP Employee
NXP Employee

Hello,

  Considerations about unused PCIe pins will take some time.

Regards,

Yuri.

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scottgauche
Contributor I

That is not the answer I was hoping for.

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