Unexpected variation of DDR3 timing PHY timing statuses

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Unexpected variation of DDR3 timing PHY timing statuses

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am_ge
Contributor I

Hello, we are nearing completion of a design using the i.MX535, and did a comparison of the DDR configuration registers to ensure no changes were accidentally made as OS patches have been applied since we last performed DDR stress testing. All of the DDR registers are the same with the following two exceptions:

  • Register ESDCTL_PDCMPR2, bits 30–24 PHY_CA_DL_UNIT (register changed from 0x1b400000 to 0x1e400000)
  • Register ESDCTL_MUR, bits 25–16 MU_UNIT_DEL_NUM (register changed from 0x006d0000 to 0x00760000)

It appears both of these bit fields are status / read only, and we'd like to determine if this difference would normally be expected when none of the other DDR configuration parameters have changed. Could it solely be a function of board-to-board variation?

Thanks - Andrew

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi  Andrew

yes this is right, it may be a function of chip and board-to-board variation.

Calibration is described in AN4466 i.MX53 DDR Calibration
https://www.nxp.com/docs/en/application-note/AN4466.pdf

Best regards
igor
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