Undervoltage Detection for a system with PF0100 and iMX6Q

[atillametetured]

Greetings,

For our custom hardware we are trying to figure out how undervoltage detection can be implemented in a system where PF0100 is feeding iMX6. I know that PF0100 has an undervolta detection at its input where it detects if Vin drops below a treshold it switches to coin cell mode but how about its outputs? What happens when say SW1A/B goes lower then intended. How can we avoid damage to the iMX6 in this case. iMX6 reference manul says REG0_BO_OFFSET, REG1_BO_OFFSET define the brown out level where maximum it can be set to 0.175V (111). I want to make sure I understand this correct, when CORE voltage level goes 0.175V below the internally programmed voltage level, the BoD is triggered and a RESET occurs. Is this correct?

If above statement is correct, the PMIC should be aware of this I assume and assert RESETBMCU low? And when the interrupt is cleared, PMIC again should be aware of this so it can deassert RESETBMCU so that through POR, iMX6 can leave the reset state. What is the right way that PMIC knows about the state of the Interrupt generated by the BoD?

Also there are two fields controlling the xPU BoD. Why is this so? (REG2_BO_OFFSET and REG1_BO_OFFSET)

Best Regards,

Mete

[art]

There are three so-called digital domain linear voltage regulators within the Power Management Unit (PMU) of i.MX6Q, they are denoted as REG0, REG1 and REG2 and provide the power to the ARM core, VPU/GPU and the rest of the SoC power domains, correspondingly. The brownout level can be set up individually for each of these regulators. When the input voltage of any of these regulators drops down below its configured brownout level, an interrupt is signalled to the CPU core to make it able to put the system into the safe state. In this case, there is no signaling between the i.MX6Q on-chip PMU and PF0100 PMIC.

Have a great day,
Artur

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