Unable to use breakpoints on iMX7D when firmware placed in OCRAM...

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Unable to use breakpoints on iMX7D when firmware placed in OCRAM...

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dry
Senior Contributor I

Hello,

I'm using iMX7D (Sabre board, or other with same SoC), and Segger's JLink for JTAG debugger.

I'm using M4's BSP as provided by NXP, with FreeRTOS: FreeRTOS_BSP_1.0.1_iMX7D.

I have problem with debugging applications when I link & place the code into OCRAM.  Refer to provided by NXP sample linker script in the BSP - MCIMX7D_M4_ocram.ld

Using the provided in the BSP Hello world sample, if linked to OCRAM, the code will run, but I cannot set breakpoints & debug because, once any of the breakpoints are hit starting from main(), the CPU will not run further, it will just stay halted on teh break point.

The culprit appears the cache usage. Ref. SystemInit() in system_MCIMX7D_M4.c:

......

/* Initialize Cache */
/* Enable System Bus Cache */
/* set command to invalidate all ways, enable write buffer
and write GO bit to initiate command */
LMEM_PSCCR = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
LMEM_PSCCR |= LMEM_PSCCR_GO_MASK;
/* wait until the command completes */
while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK);
/* Enable cache, enable write buffer */
LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
__DSB();
__ISB();

......

If I disable / skip entirely this cache initialization, then the breakpoints are working again.

Any help with this issue?  How do I keep using Cache, yet also able to actually debug the code ...

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bernhardfink
NXP Employee
NXP Employee

There is already thread about a similar topic, maybe it helps:

https://community.nxp.com/message/879246 

Regards,

Bernhard.

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dry
Senior Contributor I

Thanks Bernhard,

The issue looks same. But I don't see atm anyone got an answer of how to avoid it or 'fix' it.

Will read in details.

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Carlos_Musich
NXP Employee
NXP Employee

Hi D. RY,

Do you see this behavior only when running from OCRAM? Have you tried a different debugger?

Carlos

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dry
Senior Contributor I

Hi Carlos,

The memory I tried:  TCM, and OCRAM. In both scenarios, all linker maps exactly as from NXP examples.

Problem encountered when using OCRAM, as described above and on the thread Berhhard referred to - looks exactly same issue.

No problems with TCM.

I do not have other HW debugger to try. 

Have not tested with DDR mapping. I would expect that, if the cache'able 2MB area is used it will have the same issue.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi D. RY

may be useful to look at segger specific M4 issues with cache usage on i.MX6SX

[SOLVED] DEBUGGING doesn't work in external RAM, but in internal RAM - J-Link/Flasher related - SEGG...

Best regards
igor

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dry
Senior Contributor I

Hi Igor,

Yes thank you.

From following the discussion on that thread and what Segger reply was, the issue is the LMEM and the cache. 

So the system cache init code I pasted needs to be disabled to use J-Link.  They also say you need to disable code cache but in my tests so far I didn't see it improving anything.  System cache is the one.


Bernhard, Carlos, Igor - thanks for help.

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